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公开(公告)号：US08537601B2
公开(公告)日：2013-09-17
申请号：US13543779
申请日：2012-07-06
IPC分类号： G11C11/24
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A DRAM controller component generates a timing signal and transmits, to a DRAM, write data that requires a first time interval to propagate from the DRAM controller component to the DRAM and to be sampled by the DRAM on one or more edges of the timing signal, a clock signal that requires a second time interval to propagate from the DRAM controller component to the DRAM, and a write command, associated with the write data, to be sampled by the DRAM on one or more edges of the clock signal. The DRAM controller component includes series-coupled delay elements to generate respective incrementally delayed signals, and a multiplexer to select one of the delayed signals to time the transmission of the write data, such that transmission of the write data is delayed based on a difference between the first time interval and the second time interval.
摘要翻译： DRAM控制器部件产生定时信号，并且向DRAM发送需要第一时间间隔从DRAM控制器部件传播到DRAM并由DRAM在定时信号的一个或多个边缘进行采样的写入数据， 需要第二时间间隔从DRAM控制器部件传播到DRAM的时钟信号以及与写入数据相关联的写入命令，以由DRAM在时钟信号的一个或多个边缘上采样。 DRAM控制器组件包括串联耦合的延迟元件以产生相应的递增延迟的信号，以及多路复用器，用于选择延迟信号中的一个来对写入数据进行传输，以便写入数据的传输基于 第一时间间隔和第二时间间隔。
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公开(公告)号：US08214616B2
公开(公告)日：2012-07-03
申请号：US11754995
申请日：2007-05-29
IPC分类号： G06F13/36
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data suing a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译： 公开了一种存储器控制器。 在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一 根据与时钟信号的第一次转换相关的预定定时关系，存储器件;以及第三发送器，输出第二数据，该第二数据产生第二定时偏置，使得第二数据按照预定定时到达第二存储器件 关于时钟信号的第二转换。
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3.发明授权Method and apparatus for coordinating memory operations among diversely-located memory components 有权用于在不同位置的存储器组件之间协调存储器操作的方法和装置公开(公告)号：US07225311B2
公开(公告)日：2007-05-29
申请号：US10732533
申请日：2003-12-11
IPC分类号： G06F13/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory controller is disclosed. In one particular exemplary embodiment, the memory controller may comprise a first transmitter to output first and second write commands synchronously with respect to a clock signal, a second transmitter to output first data using a first timing offset such that the first data arrives at a first memory device in accordance with a predetermined timing relationship with respect to a first transition of the clock signal, and a third transmitter to output second data using a second timing offset such that the second data arrives at a second memory device in accordance with a predetermined timing relationship with respect to a second transition of the clock signal.
摘要翻译： 公开了一种存储器控制器。 在一个特定的示例性实施例中，存储器控制器可以包括：第一发射器，用于相对于时钟信号同步地输出第一和第二写入命令;第二发射器，使用第一定时偏移来输出第一数据，使得第一数据到达第一 根据与时钟信号的第一次转换相关的预定定时关系，以及第三发送器，使用第二定时偏移来输出第二数据，使得第二数据根据预定定时到达第二存储器装置 关于时钟信号的第二转换。
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公开(公告)号：US07225292B2
公开(公告)日：2007-05-29
申请号：US11219096
申请日：2005-09-01
IPC分类号： G06F12/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory module having a termination component. The memory module includes multiple memory devices, a termination component, a control signal path and multiple data signal paths. The control signal path is coupled to each of the memory devices and the termination component, and extends along the memory devices such that signals propagating on the control signal path propagate past each of the memory devices in succession before reaching the termination component. A unique set of data signal paths is coupled to each of the memory devices.
摘要翻译： 一种具有端接部件的存储器模块。 存储器模块包括多个存储器件，终端元件，控制信号路径和多个数据信号路径。 控制信号路径被耦合到每个存储器件和终端元件，并且沿着存储器件延伸，使得在控制信号路径上传播的信号在到达终端元件之前连续传播通过每个存储器件。 一组唯一的数据信号路径耦合到每个存储器件。
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5.发明授权Method, system and memory controller utilizing adjustable write data delay settings 有权方法，系统和内存控制器利用可调写入数据延迟设置公开(公告)号：US07210016B2
公开(公告)日：2007-04-24
申请号：US11281184
申请日：2005-11-15
IPC分类号： G06F13/20
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A method, system and memory controller that uses adjustable write data delay settings. The memory controller includes control transmit circuitry, data transmit circuitry and timing circuitry. The control circuitry transmits a control signal to multiple memory devices via a shared control signal path. The data transmit circuitry transmits data signals to the memory devices via respective data signal paths. The timing circuitry delays transmission of data signals on each of the data signal paths by a respective time interval that is based, at least in part, on a time required for the control signal to propagate on the control signal path from the memory controller to a respective one of the memory devices.
摘要翻译： 一种使用可调写入数据延迟设置的方法，系统和存储器控制器。 存储器控制器包括控制发射电路，数据发射电路和定时电路。 控制电路通过共享控制信号路径将控制信号发送到多个存储器件。 数据发送电路经由各自的数据信号路径向存储器件发送数据信号。 定时电路延迟每个数据信号路径上的数据信号的传输相应的时间间隔，该时间间隔至少部分地基于控制信号在从存储器控制器到控制信号路径的传播所需的时间 相应的一个存储器件。
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6.发明授权Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权增加具有不匹配内存模块的每个模块内存系统带宽的技术公开(公告)号：US07073035B2
公开(公告)日：2006-07-04
申请号：US11100386
申请日：2005-04-07
IPC分类号： G06F12/00
CPC分类号： G06F13/1684 , G11C8/16
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译： 公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。 在一个示例性实施例中，通过用于控制对存储器模块的访问的存储器控制器来实现这些技术，其中存储器模块具有存储器组件，存储器组件具有用于在其中存储数据的存储器核心。 存储器控制器包括用于提供对存储器模块的访问的第一组接口连接和用于提供对存储器模块的访问的第二组接口连接。 存储器控制器还包括用于向存储器模块提供存储器访问信号的存储器访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可访问 通过第二组接口连接，以及第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接来访问。
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7.发明授权Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules 有权增加具有不匹配内存模块的每个模块内存系统带宽的技术公开(公告)号：US06769050B1
公开(公告)日：2004-07-27
申请号：US09948906
申请日：2001-09-10
IPC分类号： G06F1200
CPC分类号： G06F13/1684 , G11C8/16
摘要： Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules are disclosed. In one exemplary embodiment, the techniques are realized through a memory controller for controlling access to a memory module, wherein the memory module has a memory component with a memory core for storing data therein. The memory controller comprises a first set of interface connections for providing access to the memory module, and a second set of interface connections for providing access to the memory module. The memory controller also comprises memory access circuitry for providing memory access signals to the memory module for selecting between a first mode wherein a first portion of the memory core is accessible through the first set of interface connections and a second portion of the memory core is accessible through the second set of interface connections, and a second mode wherein both the first portion and the second portion of the memory core are accessible through the first set of interface connections.
摘要翻译： 公开了用于增加具有不匹配的存储器模块的每模块模块存储器系统中的带宽的技术。 在一个示例性实施例中，通过用于控制对存储器模块的访问的存储器控制器来实现这些技术，其中存储器模块具有存储器组件，存储器组件具有用于在其中存储数据的存储器核心。 存储器控制器包括用于提供对存储器模块的访问的第一组接口连接和用于提供对存储器模块的访问的第二组接口连接。 存储器控制器还包括用于向存储器模块提供存储器访问信号的存储器访问电路，用于在第一模式之间进行选择，其中存储器核心的第一部分可通过第一组接口连接访问，并且存储器核心的第二部分可访问 通过第二组接口连接，以及第二模式，其中存储器核心的第一部分和第二部分都可通过第一组接口连接来访问。
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公开(公告)号：US20130230122A1
公开(公告)日：2013-09-05
申请号：US13846413
申请日：2013-03-18
IPC分类号： H04L7/00
CPC分类号： H04L7/0016 , G11C7/04 , G11C2207/2254 , H04L7/0087 , H04L7/0091 , H04L7/033 , H04L7/10 , H04L25/0292 , H04L25/12
摘要： A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.
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公开(公告)号：US08412906B2
公开(公告)日：2013-04-02
申请号：US13365890
申请日：2012-02-03
CPC分类号： G06F13/1678 , G06F12/04 , G06F12/06 , G06F12/0646 , G06F13/1657 , G06F13/4022 , G11C5/02 , G11C5/025 , G11C5/04 , G11C5/06 , G11C5/063 , G11C7/1006 , G11C7/1045 , G11C7/1048 , G11C7/106 , G11C7/1072 , G11C7/1087 , G11C8/06 , G11C11/4087 , G11C11/4097 , G11C2207/105 , G11C2207/108 , H05K1/117 , H05K1/14 , H05K2201/09954 , H05K2201/10189 , Y02D10/14
摘要： Described are memory apparatus organized in memory subsections and including configurable routing to support multiple data-width configurations. Relatively narrow width configurations load fewer sense amplifiers, resulting in reduced power usage for relatively narrow memory configurations. Also described are memory controllers that convey width selection information to configurable memory apparatus and support point-to-point data interfaces for multiple width configurations.
摘要翻译： 描述了组织在存储器子部分中并且包括可配置路由以支持多个数据宽度配置的存储器设备。 相对窄的宽度配置加载较少的读出放大器，导致相对较窄的存储器配置的功率消耗减少。 还描述了将宽度选择信息传送到可配置的存储装置并支持多个宽度配置的点对点数据接口的存储器控制器。
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公开(公告)号：US08395951B2
公开(公告)日：2013-03-12
申请号：US13461923
申请日：2012-05-02
IPC分类号： G11C7/00
CPC分类号： G11C11/4076 , G06F1/06 , G06F1/105 , G06F1/12 , G06F3/0604 , G06F3/0658 , G06F3/0673 , G06F13/1684 , G06F13/1689 , G06F13/1694 , G06F13/4086 , G11C5/063 , G11C7/04 , G11C7/1051 , G11C7/1072 , G11C7/1078 , G11C7/22 , G11C7/222 , G11C8/18 , G11C11/409 , G11C11/4096 , G11C29/02 , G11C29/022 , G11C29/023 , G11C29/028 , G11C29/50008 , G11C29/50012
摘要： A memory component having a first and second interface. The first interface is provided to sample address information in response to a first clock signal. The first interface includes inputs to sample at least two bits of the address information in succession during a clock cycle of the first clock signal. The second interface is provided to sample data in response to a second clock signal, having a frequency that is at least twice the frequency of the first clock signal. The second interface includes inputs to sample at least two bits of data in succession during a clock cycle of the second clock signal.
摘要翻译： 一种具有第一和第二接口的存储器组件。 提供第一接口以响应于第一时钟信号对地址信息进行采样。 第一接口包括在第一时钟信号的时钟周期期间连续地采样地址信息的至少两个比特的输入。 提供第二接口以响应于第二时钟信号采样数据，其具有至少是第一时钟信号频率的两倍的频率。 第二接口包括在第二时钟信号的时钟周期期间连续采样至少两位数据的输入。
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