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    Trench MOSFET device with polycrystalline silicon source contact structure
    1.
    发明申请
    Trench MOSFET device with polycrystalline silicon source contact structure 失效
    沟槽MOSFET器件，具有多晶硅源接触结构

    公开(公告)号：US20050062075A1

    公开(公告)日：2005-03-24

    申请号：US10983490

    申请日：2004-11-08

    申请人： Fwu-Iuan Hshieh ,  Koon So ,  John Amato ,  Yan Tsui

    发明人： Fwu-Iuan Hshieh ,  Koon So ,  John Amato ,  Yan Tsui

    IPC分类号： H01L21/336 ,  H01L29/10 ,  H01L29/45 ,  H01L29/78 ,  H01L31/062

    CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/456

    摘要： A trench MOSFET transistor device and a method of making the same. The device comprises: (a) a silicon substrate of first conductivity type; (b) a silicon epitaxial layer of first conductivity type over the substrate, the epitaxial layer having a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type provided within an upper portion of the body region and adjacent the trench; (h) an upper region of second conductivity type within an upper portion of the body region and adjacent the source region, the upper region having a higher majority carrier concentration than the body region; and (i) a source contact region disposed on the epitaxial layer upper surface, wherein the source contact region comprises a doped polycrystalline silicon contact region in electrical contact with the source region as well as an adjacent metal contact region in electrical contact with the source region and with the upper region.

    摘要翻译： 沟槽MOSFET晶体管器件及其制造方法。 该装置包括：（a）第一导电类型的硅衬底; （b）在衬底上的第一导电类型的硅外延层，所述外延层具有比衬底更低的载流子浓度; （c）从外延层的上表面延伸到外延层中的沟槽; （d）衬在所述沟槽的至少一部分上的绝缘层; （e）邻近绝缘层的沟槽内的导电区域; （f）第二导电类型的体区，设置在所述外延层的上部并且与所述沟槽相邻; （g）第一导电类型的源极区域，设置在所述主体区域的上部并且邻近所述沟槽; （h）第二导电类型的上部区域，在所述主体区域的上部并且邻近所述源极区域，所述上部区域具有比所述身体区域更高的载流子浓度; 和（i）设置在所述外延层上表面上的源极接触区域，其中所述源极接触区域包括与所述源极区域电接触的掺杂多晶硅接触区域以及与所述源极区域电接触的相邻金属接触区域 和上部区域。

    Method and structure for improving the gate resistance of a closed cell trench power MOSFET
    3.
    发明申请
    Method and structure for improving the gate resistance of a closed cell trench power MOSFET 审中-公开
    提高封闭沟槽功率MOSFET栅极电阻的方法和结构

    公开(公告)号：US20050040459A1

    公开(公告)日：2005-02-24

    申请号：US10647029

    申请日：2003-08-22

    申请人： John Amato ,  Badredin Fatemizadeh ,  Ali Salih ,  Shamsul Khan

    发明人： John Amato ,  Badredin Fatemizadeh ,  Ali Salih ,  Shamsul Khan

    IPC分类号： H01L20060101 ,  H01L21/336 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7813 ,  H01L29/4236 ,  H01L29/4238

    摘要： A closed cell trench power MOSFET has a trench (54) running in first and second perpendicular directions through a body region (48) and extending into an epitaxial region (46). The trenches meet to form intersections (16). A polysilicon layer (58) is deposited in the trench. A photoresist pattern (60) is formed over the intersections to inhibit removal of the conductive material from the trench in and around the intersection areas. The process of inhibiting removal of the conductive material over the intersection areas of the trench prevents formation of a depression in the polysilicon in and around the intersection which would increase resistivity in the gate region. The goal of preventing formation of depressions in the polysilicon can also be achieved by making the polysilicon thicker on the intersections prior to the etching process and by making the trenches narrower in and around the intersections.

    摘要翻译： 闭孔沟槽功率MOSFET具有穿过体区（48）的第一和第二垂直方向上延伸并延伸到外延区域（46）中的沟槽（54）。 壕沟相交，形成十字路口（16）。 多晶硅层（58）沉积在沟槽中。 在交叉点之上形成光致抗蚀剂图案（60），以阻止导电材料从交叉区域内和周围的沟槽移除。 阻止在沟槽的交叉区域上去除导电材料的过程防止在交叉点中和周围的多晶硅中形成凹陷，这将增加栅极区域中的电阻率。 防止在多晶硅中形成凹陷的目的还可以通过在蚀刻工艺之前使交叉点上的多晶硅变厚，并且通过在交叉点内和周围使沟槽变窄来实现。

    Continuous molding machine
    5.
    发明授权
    Continuous molding machine 失效
    连续成型机

    公开(公告)号：US4025267A

    公开(公告)日：1977-05-24

    申请号：US628798

    申请日：1975-11-04

    申请人： John Amato ,  Charles Hirsch ,  Louis Siegel

    发明人： John Amato ,  Charles Hirsch ,  Louis Siegel

    IPC分类号： A21B5/02 ,  B29C7/00

    CPC分类号： A21B5/02

    摘要： A continuous molding machine particularly adapted for but not limited, in principle, to the making of waffles includes a lower conveyor carrying a plurality of forms each constituting a first part of a respective two-part split mold, a second conveyor carrying a plurality of forms each constituting the other part of the respective split molds and means for guiding the respective conveyors in respective paths so that the first and second mold parts are carried from spaced apart positions to positions in which the parts meet in registry and each of the molds defined by the parts is thereby closed and then the first and second mold parts are carried away from each other again so that each of the molds is opened. The conveyors carrying the mold parts may be passed through an oven to different extents so that the respective conveyors are heated differently and means are provided for aligning the mating mold parts despite different thermal expansions of the conveyors. Means may be provided for facilitating or positively effecting partial opening of the closed molds to permit the release of gases or vapors contained in the molds. Means may be provided for permitting the closed molds to partially open to release gases or vapors contained therein only upon the reaching of a predetermined minimum gas or vapor pressure in the mold. Means may be provided for swinging the mold parts out of the plane of the conveyor on which they are carried in order to facilitate such operations as cleaning of the mold parts.

    摘要翻译： 原则上特别适用于但不限于制造华夫饼的连续成型机包括：下部输送器，其承载多个形式，每个形式构成相应的两部分分割模具的第一部分，第二传送带承载多个形式 每个构成各个分开模具的另一部分，以及用于在各个路径中引导各个输送机的装置，使得第一和第二模具部件从间隔开的位置运送到部件相对于对准的位置，并且每个模具由 部件因此被关闭，然后第一和第二模具部件被再次彼此远离，使得每个模具都被打开。 携带模具部件的输送机可以通过烘箱到不同程度，使得相应的输送机被不同地加热，并且提供用于对准配合的模具部件的装置，尽管传送带的不同的热膨胀。 可以提供用于促进或积极地实现封闭模具的部分打开以允许包含在模具中的气体或蒸汽的释放的装置。 可以提供用于允许封闭模具部分打开以释放仅在模具中达到预定的最小气体或蒸汽压力时所含的气体或蒸汽的装置。 可以提供用于将模具部件摆放在其所携带的输送机的平面内的装置，以便于诸如清洁模具部件的操作。

    Low cost method of fabricating shallow junction, Schottky semiconductor devices
    7.
    发明授权
    Low cost method of fabricating shallow junction, Schottky semiconductor devices 失效
    低成本的方法制造浅结，肖特基半导体器件

    公开(公告)号：US5635414A

    公开(公告)日：1997-06-03

    申请号：US409762

    申请日：1995-03-28

    申请人： Gregory Zakaluk ,  Dennis Garbis ,  Willem Einthoven ,  Joseph Chan ,  Jack Eng ,  Jun Wu ,  John Amato

    发明人： Gregory Zakaluk ,  Dennis Garbis ,  Willem Einthoven ,  Joseph Chan ,  Jack Eng ,  Jun Wu ,  John Amato

    IPC分类号： H01L21/20 ,  H01L21/285 ,  H01L21/322 ,  H01L21/265

    CPC分类号： H01L21/28537 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/3221 ,  Y10S438/974

    摘要： Significant reduction in the cost of fabrication of shallow junction, Schottky or similar semiconductor devices without sacrifice of functional characteristics, while at the same time achieving the advantages is achieved, after the non-polishing cleaning step is essentially performed, by subjecting the substrate to conditions which move disadvantageous factors within said substrate into a space substantially at said surface, followed by substantially removing said factor-containing space from said substrate chemical removal step, followed etching and vapor deposition steps. Although these new steps add time, and therefore cost, to the overall process, the devices under discussion when produced by known industry processes require yet more time, and involve yet more expense, so that the total process represents a substantial reduction in the cost of their manufacture while producing devices which are the equivalent or superior in electrical performance to such devices which are made by known industry processes.

    摘要翻译： 在不牺牲功能特性的情况下显着降低了制造浅结，肖特基或类似半导体器件的成本，同时实现了在基本上执行非抛光清洁步骤之后，通过使基板经受条件 其将所述衬底内的不利因素移动到基本上位于所述表面的空间中，然后在蚀刻和气相沉积步骤之后基本上从所述衬底化学品去除步骤中除去所述含因子空间。 虽然这些新的步骤为整个过程增加了时间，因此增加了成本，但由已知行业流程生产的正在讨论的设备需要更多的时间，并且涉及更多的费用，因此整个过程将大大降低成本 它们的制造同时生产与通过已知工业方法制造的这种装置相当或优越的电气性能的装置。

    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like
    8.
    发明授权
    Low cost method of fabricating transient voltage suppressor semiconductor devices or the like 失效
    制造瞬态电压抑制半导体器件等的低成本方法

    公开(公告)号：US06248651B1

    公开(公告)日：2001-06-19

    申请号：US09103731

    申请日：1998-06-24

    申请人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    发明人： Jack Eng ,  Joseph Chan ,  Gregory Zakaluk ,  John Amato ,  Dennis Garbis

    IPC分类号： H01L21225

    CPC分类号： H01L21/304 ,  H01L21/2252

    摘要： Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

    摘要翻译： 对于产生PN结的杂质的扩散和深度的严格要求的瞬态电压抑制器半导体器件和其他半导体器件可以以惊人的低成本制造，而不牺牲功能特性，通过使衬底经受磨削过程，导致表面缺少抛光 从而消除耗时且因此昂贵的常规抛光操作，然后从固体杂质源将所需的杂质扩散到衬底中。