公开(公告)号：US5904525A

公开(公告)日：1999-05-18

申请号：US646593

申请日：1996-05-08

申请人： Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Bosco Lan ,  Jowei Dun

发明人： Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Bosco Lan ,  Jowei Dun

IPC分类号： H01L21/26 ,  H01L21/336 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L29/78 ,  H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7813 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/0696 ,  Y10S148/126

摘要： A method for forming a trenched DMOS transistor with deep body regions that occupy minimal area on an epitaxial layer formed on a semiconductor substrate. A first oxide layer is formed over the epitaxial layer and patterned to define deep-body areas beneath which the deep body regions are to be formed. Next, diffusion-inhibiting regions of the first conductivity type are formed in each of the deep-body areas before forming a second oxide layer covering the deep-body areas and the remaining portion of the first oxide layer. Portions of the second oxide layer are then removed to expose the centers of the diffusion inhibiting regions, leaving the first oxide layer and oxide sidewall spacers from the second oxide layer to cover the peripheries of the diffusion-inhibiting regions. A deep-body diffusion of a second conductivity type is then performed, resulting in the formation of deep body regions in the epitaxial layer between the sidewall spacers. The peripheries of the diffusion-inhibiting regions covered by the remaining portions of the first and second oxide layers inhibit lateral diffusion of the deep body diffusions without significantly inhibiting diffusion depth.

摘要翻译： 一种用于形成具有在半导体衬底上形成的外延层上占据最小面积的深体区的沟槽DMOS晶体管的方法。 第一氧化物层形成在外延层上并且被图案化以限定将在其下形成深体区域的深体区域。 接下来，在形成覆盖深体区域的第二氧化物层和第一氧化物层的剩余部分之前，在每个深体区域中形成第一导电类型的扩散抑制区域。 然后去除第二氧化物层的部分以暴露扩散抑制区域的中心，从第二氧化物层留下第一氧化物层和氧化物侧壁间隔物以覆盖扩散抑制区域的周边。 然后执行第二导电类型的深体扩散，导致在侧壁间隔件之间的外延层中形成深体区。 由第一和第二氧化物层的剩余部分覆盖的扩散抑制区域的周边阻止深体扩散的横向扩散，而不显着抑制扩散深度。

公开(公告)号：US5767578A

公开(公告)日：1998-06-16

申请号：US634957

申请日：1996-04-19

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun ,  Hans-Jurgen Fusser ,  Reinhard Zachai

IPC分类号： H01L23/29 ,  H01L23/367 ,  H01L23/373 ,  H01L23/34

CPC分类号： H01L23/3672 ,  H01L23/29 ,  H01L23/3732 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The passivation layer is a CVD diamond film which provides both electrical insulation and thermal conductivity. The substrate backside surface is removed (by grinding and/or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 钝化层是提供电绝缘和导热性的CVD金刚石膜。 去除衬底背面（通过研磨和/或CMP）以暴露沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片以两种版本刻成模具，而不需要进一步的包装。

公开(公告)号：US5757081A

公开(公告)日：1998-05-26

申请号：US603512

申请日：1996-02-20

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L23/48

CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

摘要翻译： 集成电路芯片具有芯片每个部分的全沟槽绝缘隔离。 最初，芯片基板具有常规的厚度并且在其中形成半导体器件。 在蚀刻衬底中的沟槽并用电介质材料填充沟槽之后，将散热器盖附着到衬底前侧表面上的钝化层。 通过研磨或CMP去除衬底背面以露出沟槽的底部。 这完全隔离了模具的每个部分，并消除了沟槽底部的机械应力。 此后，漏极或集电极电触点设置在基板背面上。 在倒装芯片版本中，前端电触点延伸穿过前侧钝化层到散热器盖。 在表面安装型式中，通孔穿过衬底被蚀刻，表面安装柱形成在通孔上，以接触前侧电触点并提供衬底背面上的所有电触头。 然后将晶片刻成两个版本的模具，无需进一步包装。

公开(公告)号：US5753529A

公开(公告)日：1998-05-19

申请号：US444660

申请日：1995-05-19

申请人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

发明人： Mike F. Chang ,  King Owyang ,  Fwu-Iuan Hshieh ,  Yueh-Se Ho ,  Jowei Dun

IPC分类号： H01L23/367 ,  H01L23/373 ,  H01L21/302

CPC分类号： H01L23/3672 ,  H01L23/3738 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/14 ,  Y10S148/135 ,  Y10S438/928 ,  Y10S438/977

摘要： An integrated circuit chip has full trench dielectric isolation of each portion of the chip. Initially the chip substrate is of conventional thickness and has semiconductor devices formed in it. After etching trenches in the substrate and filling them with dielectric material, a heat sink cap is attached to the passivation layer on the substrate front side surface. The substrate backside surface is removed (by grinding or CMP) to expose the bottom portion of the trenches. This fully isolates each portion of the die and eliminates mechanical stresses at the trench bottoms. Thereafter drain or collector electrical contacts are provided on the substrate backside surface. In a flip chip version, frontside electrical contacts extend through the frontside passivation layer to the heat sink cap. In a surface mount version, vias are etched through the substrate, with surface mount posts formed on the vias, to contact the frontside electrical contacts and provide all electrical contacts on the substrate backside surface. The wafer is then scribed into die in both versions without need for further packaging.

公开(公告)号：US06281146B1

公开(公告)日：2001-08-28

申请号：US09396517

申请日：1999-09-15

申请人： Ying-Lang Wang ,  Hui-Ling Wang ,  Jowei Dun ,  Szu-An Wu

发明人： Ying-Lang Wang ,  Hui-Ling Wang ,  Jowei Dun ,  Szu-An Wu

IPC分类号： H01L2131

CPC分类号： H01L21/02164 ,  C23C16/402 ,  C23C16/5096 ,  H01L21/02211 ,  H01L21/02274 ,  H01L21/31612

摘要： A method for forming a microelectronic layer. There is first provided a substrate. There is then formed over the substrate the microelectronic layer while employing a plasma enhanced chemical vapor deposition (PECVD) method employing a source material gas and a carrier gas, wherein there is employed a sufficiently low plasma power, a sufficiently low source material gas:carrier gas flow rate ratio and a sufficiently high carrier gas atomic mass such that the microelectronic layer is formed with enhanced film thickness uniformity. The method may be employed for forming ion implant screen layers, such as silicon oxide ion implant screen layers, with enhanced film thickness uniformity.

摘要翻译： 一种形成微电子层的方法。 首先提供基板。 然后在采用使用源材料气体和载气的等离子体增强化学气相沉积（PECVD）方法的基板上形成微电子层，其中采用足够低的等离子体功率，足够低的源材料气体：载体 气体流量比和足够高的载气原子质量，使得微电子层形成为具有增强的膜厚均匀性。 该方法可用于形成具有增强的膜厚度均匀性的离子注入屏幕层，例如氧化硅离子注入屏幕层。

公开(公告)号：US06395635B1

公开(公告)日：2002-05-28

申请号：US09206741

申请日：1998-12-07

申请人： Ying-Lang Wang ,  Jowei Dun

发明人： Ying-Lang Wang ,  Jowei Dun

IPC分类号： H01L21302

CPC分类号： H01L21/31053 ,  H01L21/3212

摘要： A CMP process is provided for the reduction of tungsten damascene residue and the elimination of surface scratch within the surface that is being polished. A three step polishing procedure of the ILD is followed by a two step buffing procedure of the ILD. The three step polishing procedure reduces the device defect count by eliminating damascene residue from the polished surface. The two step buffing procedure reduces micro scratch within the polished surface thus improving device throughput. A two step buffing procedure is applied to the IMD. Oxide buffing is applied and consists of a three step polishing procedure followed by a two step buffing procedure.

摘要翻译： 提供了一种CMP工艺，用于减少钨镶嵌残余物并消除正在抛光的表面内的表面划痕。 ILD的三步抛光程序之后是ILD的两步抛光程序。 三步抛光程序通过从抛光表面去除镶嵌残留物来减少设备缺陷计数。 两步抛光程序减少抛光表面内的微刮痕，从而提高设备的生产能力。 对IMD应用两步抛光程序。 应用氧化物抛光，并由三步抛光程序组成，其后是两步抛光程序。

公开(公告)号：US06479881B2

公开(公告)日：2002-11-12

申请号：US09882678

申请日：2001-06-18

申请人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

发明人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

IPC分类号： H01L2900

CPC分类号： H01L21/76801 ,  H01L21/31612 ,  H01L21/76837 ,  Y10S438/937

摘要： A semiconductor wafer having a double inter-metal dielectric layer formed in the gaps of and on closely. spaced metal interconnection circuitry. The double dielectric layer is formed by an in situ low temperature two step deposition HDP-CVD process separated by a cool-down period. The low temperature process mitigates metal line defects such as distortion or warping caused by heat generated during the process of filling gaps having aspect ratios greater than 2. The double dielectric layer is composed of Group IV materials, silicon being the preferred material. These double layers may be individually doped. Titanium nitride layers, present as by-products of seeding and anti-reflective coatings serve to reduce electro-migration of the metal circuitry.

摘要翻译： 一种半导体晶片，其具有形成在间隙中并紧密地形成的双金属介电层。 间隔金属互连电路。 双电介质层通过在冷却期间分离的原位低温两步沉积HDP-CVD工艺形成。 低温处理减轻了金属线缺陷，例如在填充具有大于2的纵横比的间隙的过程中产生的热引起的变形或翘曲。双电介质层由第IV族材料组成，硅是优选的材料。 这些双层可以单独掺杂。 作为接种和抗反射涂层的副产物存在的氮化钛层用于减少金属电路的电迁移。

公开(公告)号：US5956609A

公开(公告)日：1999-09-21

申请号：US907985

申请日：1997-08-11

申请人： Jiun-Chung Lee ,  Hui-Ling Wang ,  Jowei Dun ,  Ken-Shen Chou

发明人： Jiun-Chung Lee ,  Hui-Ling Wang ,  Jowei Dun ,  Ken-Shen Chou

IPC分类号： H01L21/768 ,  H01L21/443

CPC分类号： H01L21/76876 ,  H01L21/76843 ,  H01L21/76877

摘要： A method is described for improving the step coverage of tungsten interconnects and plugs when deposited at low temperatures into contact/via openings having high aspect ratios. The depositions are made at pressures between 4.5 and 100 Torr in a CVD tool. The method includes a first nucleation step, and a second step for filling the contact/via openings wherein deposition conditions favor good step coverage. For forming an interconnect and a third deposition step, providing moderate step coverage and low stress, is used to build up the interconnect. The high pressures permit deposition at practical rates at low temperatures. In addition the high pressures also permit application of backside gas pressure to the wafer during deposition, thereby improving the thermal contact between the wafer and the heated substrate holder. This contributes significantly to stress reduction and improved step coverage.

摘要翻译： 描述了一种用于在低温沉积到具有高纵横比的接触/通孔开口时改善钨互连和插塞的台阶覆盖率的方法。 沉积物在CVD工具中的压力为4.5至100托之间。 该方法包括第一成核步骤和用于填充接触/通孔的第二步骤，其中沉积条件有利于良好的步骤覆盖。 为了形成互连和第三沉积步骤，提供适度的阶梯覆盖和低应力，用于建立互连。 高压允许在低温下以实际的速率沉积。 此外，高压还允许在沉积期间向晶片施加背侧气体压力，从而改善晶片和加热的衬底保持器之间的热接触。 这显着地减轻了压力并提高了台阶覆盖率。

公开(公告)号：US06291872B1

公开(公告)日：2001-09-18

申请号：US09433255

申请日：1999-11-04

申请人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

发明人： Ying-Lang Wang ,  Hway-Chi Lin ,  Jun Wu ,  Jowei Dun

IPC分类号： H01L2900

CPC分类号： H01L28/10 ,  H01F17/0013 ,  H01L27/08

摘要： Vertical type structures for integrated circuit inductors are disclosed. These vertical type inductors include the single-loop type, the parallel-loop type and the screw type, which form three different embodiments in the present invention. In the first embodiment, three-dimensional type structures, a single-loop type is utilized as an integrated circuit inductor. This inductor structure is formed on a substrate and the axis of the structure is upright to the substrate. In another embodiment according to the present invention, a parallel-loop type structure for radio frequency (RF) integrated circuit inductor is provided. A screw type structure according to this invention is the third embodiment. It features an axis that is parallel to the surface of the substrate and threads into the semiconductor device.

摘要翻译： 公开了集成电路电感器的垂直型结构。 这些垂直型电感器包括在本发明中形成三个不同实施例的单环型，并联环型和螺旋型。 在第一实施例中，采用单环型的三维型结构作为集成电路电感器。 该电感器结构形成在基板上，并且该结构的轴线垂直于基板。 在根据本发明的另一实施例中，提供了一种用于射频（RF）集成电路电感器的并联环路结构。 根据本发明的螺杆型结构是第三实施例。 它具有平行于衬底表面并进入半导体器件的轴线。

公开(公告)号：US06268274B1

公开(公告)日：2001-07-31

申请号：US09418032

申请日：1999-10-14

申请人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

发明人： Ying-Lang Wang ,  Chun-Ching Tsan ,  Jowei Dun ,  Hung-Ju Chien

IPC分类号： H01L2100

CPC分类号： H01L21/76801 ,  H01L21/31612 ,  H01L21/76837 ,  Y10S438/937

摘要： This invention provides an in situ low temperature, two step deposition HDP-CVD process separated by a cooldown period, for forming an inter-metal dielectric passivation layer for an integrated circuit structure. Said process mitigating metal line defects such as distortion or warping caused by excessive heat generated during the etching/deposition process.

摘要翻译： 本发明提供了一种在冷却期间分离的原位低温两步沉积HDP-CVD工艺，用于形成用于集成电路结构的金属间介电钝化层。 所述方法减轻金属线缺陷，例如在蚀刻/沉积工艺期间产生的过多热引起的变形或翘曲。