公开(公告)号：US09966735B2

公开(公告)日：2018-05-08

申请号：US15188419

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Cheng-Wei Cheng ,  Frank R. Libsch ,  Tak H. Ning ,  Uzma Rana ,  Kuen-Ting Shiu

IPC: H01S5/00 ,  H01S5/227 ,  H01S5/026 ,  H01S3/063 ,  H01S3/23 ,  H01S5/16 ,  H01S5/20 ,  H01S5/30 ,  H01S5/125 ,  H01S5/02 ,  H01S5/10

CPC classification number: H01S5/2275 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/026 ,  H01S5/1017 ,  H01S5/1057 ,  H01S5/125 ,  H01S5/166 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/18363 ,  H01S3/0315

Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.

公开(公告)号：US09508640B2

公开(公告)日：2016-11-29

申请号：US13940874

申请日：2013-07-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Szu-Lin Cheng ,  Keith E. Fogel ,  Edward W. Kiewra ,  Amlan Majumdar ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/00 ,  H01L23/522 ,  H01L23/485 ,  H01L21/8238 ,  H01L27/12

CPC classification number: H01L23/5226 ,  H01L21/823807 ,  H01L21/823878 ,  H01L23/485 ,  H01L27/1207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method for forming a device with a multi-tiered contact structure includes forming first contacts in via holes down to a first level, forming a dielectric capping layer over exposed portions of the first contacts and forming a dielectric layer over the capping layer. Via holes are opened in the dielectric layer down to the capping layer. Holes are opened in the capping layer through the via holes to expose the first contacts. Contact connectors and second contacts are formed in the via holes such that the first and second contacts are connected through the capping layer by the contact connectors to form multi-tiered contacts.

Abstract translation: 用于形成具有多层接触结构的器件的方法包括将通孔中的第一触点形成为第一级，在第一触点的暴露部分上形成电介质覆盖层，并在覆盖层上形成电介质层。 通孔在电介质层中向下开到封盖层。 孔通过通孔在封盖层中打开以露出第一触点。 接触连接器和第二触点形成在通孔中，使得第一和第二触点通过接触连接器通过覆盖层连接以形成多层接触。

公开(公告)号：US09337281B2

公开(公告)日：2016-05-10

申请号：US14803910

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Jack O. Chu ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/336 ,  H01L29/267 ,  H01L29/772 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/322 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/28575 ,  H01L21/3228 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

公开(公告)号：US20160301192A1

公开(公告)日：2016-10-13

申请号：US15188419

申请日：2016-06-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Cheng-Wei Cheng ,  Frank R. Libsch ,  Tak H. Ning ,  Uzma Rana ,  Kuen-Ting Shiu

IPC: H01S5/227 ,  H01S5/30 ,  H01S5/10 ,  H01S5/20

CPC classification number: H01S5/2275 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/026 ,  H01S5/1017 ,  H01S5/1057 ,  H01S5/125 ,  H01S5/166 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/18363 ,  H01S3/0315

Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.

公开(公告)号：US09236251B2

公开(公告)日：2016-01-12

申请号：US14705425

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Tak H. Ning ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/2007 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/267

Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.

公开(公告)号：US09407066B2

公开(公告)日：2016-08-02

申请号：US13949973

申请日：2013-07-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Frank R. Libsch ,  Tak H. Ning ,  Uzma Rana ,  Kuen-Ting Shiu

IPC: H01L21/00 ,  H01S5/00 ,  H01S5/227 ,  H01S5/16 ,  H01S5/02 ,  H01S5/10

CPC classification number: H01S5/2275 ,  H01S3/0637 ,  H01S3/2375 ,  H01S5/021 ,  H01S5/026 ,  H01S5/1017 ,  H01S5/1057 ,  H01S5/125 ,  H01S5/166 ,  H01S5/2018 ,  H01S5/3013 ,  H01S5/18363 ,  H01S3/0315

Abstract: III-V lasers integrated with silicon photonic circuits and methods for making the same include a three-layer semiconductor stack formed from III-V semiconductors on a substrate, where a middle layer has a lower bandgap than a top layer and a bottom layer; a mirror region monolithically formed at a first end of the stack, configured to reflect emitted light in the direction of the stack; and a waveguide region monolithically formed at a second end of the stack, configured to transmit emitted light.

Abstract translation: 与硅光子电路集成的III-V激光器及其制造方法包括由衬底上的III-V半导体形成的三层半导体叠层，其中中间层具有比顶层和底层更低的带隙; 整体地形成在所述堆叠的第一端处的反射镜区域，被构造成在所述堆叠的方向上反射发射的光; 以及波导区域，其单片地形成在所述堆叠的第二端处，被配置为透射发射的光。

公开(公告)号：US09391144B2

公开(公告)日：2016-07-12

申请号：US14725581

申请日：2015-05-29

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L29/20 ,  H01L21/02 ,  H01L29/04 ,  H01L23/528 ,  H01L27/088 ,  H01L29/205 ,  H01L33/00 ,  H01L33/12

CPC classification number: H01L29/2003 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/02658 ,  H01L23/528 ,  H01L27/088 ,  H01L29/04 ,  H01L29/045 ,  H01L29/205 ,  H01L33/007 ,  H01L33/12 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor structure including a (100) silicon substrate having a plurality openings located within the silicon substrate, wherein each opening exposes a surface of the silicon substrate having a (111) crystal plane. This structure further includes an epitaxial semiconductor material located on an uppermost surface of the (100) silicon substrate, and a gallium nitride material located adjacent to the surface of the silicon substrate having the (111) crystal plane and adjacent a portion of the epitaxial semiconductor material. The structure also includes at least one semiconductor device located upon and within the gallium nitride material and at least one other semiconductor device located upon and within the epitaxial semiconductor material.

Abstract translation: 一种半导体结构，包括具有位于硅衬底内的多个开口的（100）硅衬底，其中每个开口暴露具有（111）晶面的硅衬底的表面。 该结构还包括位于（100）硅衬底的最上表面上的外延半导体材料和位于与具有（111）晶面并且与外延半导体的一部分相邻的硅衬底的表面附近的氮化镓材料 材料。 该结构还包括位于氮化镓材料之上和之内的至少一个半导体器件和位于外延半导体材料之上和之内的至少一个其它半导体器件。