公开(公告)号：US20180053662A1

公开(公告)日：2018-02-22

申请号：US15238760

申请日：2016-08-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan PAWLAK ,  Harry J. LEVINSON

IPC: H01L21/308 ,  H01L21/306 ,  H01L29/04 ,  H01L21/02

CPC classification number: H01L21/0243 ,  H01L21/02381 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02658 ,  H01L21/30608 ,  H01L21/3081

Abstract: A method of texturing a silicon (Si) wafer and the resulting device are provided. Embodiments include forming a mask over an upper surface of a Si wafer; patterning the mask by direct-self assembly (DSA); etching the Si wafer through the patterned mask to form holes in the Si wafer; removing the mask; and etching the holes to form a textured surface in the Si wafer.

公开(公告)号：US20150061014A1

公开(公告)日：2015-03-05

申请号：US14011125

申请日：2013-08-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil JACOB ,  Murat Kerem AKARVARDAR ,  Steven John BENTLEY ,  Bartlomiej Jan PAWLAK

IPC: H01L21/764 ,  H01L21/02 ,  H01L29/78

CPC classification number: H01L21/764 ,  H01L21/02488 ,  H01L21/02587 ,  H01L21/762 ,  H01L29/66795 ,  H01L29/785

Abstract: A first semiconductor structure includes a bulk silicon substrate and one or more original silicon fins coupled to the bulk silicon substrate. A dielectric material is conformally blanketed over the first semiconductor structure and recessed to create a dielectric layer. A first cladding material is deposited adjacent to the original silicon fin, after which the original silicon fin is removed to form a second semiconductor structure having two fins that are electrically isolated from the bulk silicon substrate. A second cladding material is patterned adjacent to the first cladding material to form a third semiconductor structure having four fins that are electrically isolated from the bulk silicon substrate.

Abstract translation: 第一半导体结构包括体硅衬底和耦合到体硅衬底的一个或多个原始硅鳍片。 电介质材料保形地覆盖在第一半导体结构上并凹进以产生电介质层。 第一覆层材料沉积在原始硅鳍片附近，之后去除原始硅片以形成具有与体硅衬底电隔离的两个散热片的第二半导体结构。 第二包层材料被图案化为与第一包层材料相邻以形成具有与体硅衬底电隔离的四个散热片的第三半导体结构。

公开(公告)号：US20170179248A1

公开(公告)日：2017-06-22

申请号：US14970661

申请日：2015-12-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan PAWLAK

IPC: H01L29/423 ,  H01L21/308 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/42392 ,  B82Y10/00 ,  H01L21/3081 ,  H01L29/0673 ,  H01L29/1079 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.

公开(公告)号：US20180269191A1

公开(公告)日：2018-09-20

申请号：US15459336

申请日：2017-03-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Luke ENGLAND ,  Bartlomiej Jan PAWLAK

IPC: H01L25/16 ,  H01L25/075 ,  H01L25/00 ,  H01L33/62 ,  H01L33/32

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a micro-light emitting diode (LED) display assembly and methods of manufacture. The structure includes an interposer and a plurality of micro-LED arrays each of which include a plurality of through-vias connecting pixels of the plurality of micro-LED arrays to the interposer.

公开(公告)号：US20170098544A1

公开(公告)日：2017-04-06

申请号：US14874623

申请日：2015-10-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan PAWLAK

IPC: H01L21/225 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/26506 ,  H01L21/28518

Abstract: A method of forming a metal-silicon contact is provided. Embodiments include forming a metal layer over a substrate; forming an amorphous silicon (a-Si) capping layer over the metal layer; implanting ions to induce an athermal migration of the a-Si capping layer into the metal layer; and annealing the metal layer and the a-Si capping layer to form a metal silicide layer over the substrate.

公开(公告)号：US20170018421A1

公开(公告)日：2017-01-19

申请号：US14797531

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan PAWLAK

IPC: H01L21/02 ,  H01L29/161 ,  H01L29/201 ,  H01L21/321 ,  H01L29/06

CPC classification number: H01L21/0265 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02645 ,  H01L21/3212 ,  H01L29/0657 ,  H01L29/161 ,  H01L29/201

Abstract: A method of forming a stress relaxed buffer layer (SRB) on a textured or grooved silicon (Si) surface and the resulting device are provided. Embodiments include forming a textured surface in an upper surface of a Si wafer; epitaxially growing a low-temperature seed layer on the textured surface of the Si wafer; depositing a SRB layer over the low-temperature seed layer; and planarizing an upper surface of the SRB layer.

Abstract translation: 提供了在纹理或开槽的硅（Si）表面上形成应力松弛缓冲层（SRB）的方法，并且提供了所得到的器件。 实施例包括在Si晶片的上表面中形成纹理表面; 在Si晶片的织构化表面上外延生长低温种子层; 在低温种子层上沉积SRB层; 并平坦化SRB层的上表面。