公开(公告)号：US20160049400A1

公开(公告)日：2016-02-18

申请号：US14924486

申请日：2015-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

公开(公告)号：US20180315832A1

公开(公告)日：2018-11-01

申请号：US16028082

申请日：2018-07-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Dina H. TRIYOSO ,  Ryan SPORER

IPC: H01L29/66 ,  H01L29/786 ,  H01L21/84 ,  H01L27/12 ,  H01L29/417 ,  H01L29/06 ,  H01L29/51

CPC classification number: H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20150380409A1

公开(公告)日：2015-12-31

申请号：US14315885

申请日：2014-06-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Mitsuhiro TOGO ,  Changyong XIAO ,  Yiqun LIU ,  Dina H. TRIYOSO ,  Rohit PAL

IPC: H01L27/092 ,  H01L21/321 ,  H01L21/265 ,  H01L21/8238 ,  H01L21/324

CPC classification number: H01L27/0922 ,  H01L21/26513 ,  H01L21/32115 ,  H01L21/324 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823842 ,  H01L21/845 ,  H01L27/0924 ,  H01L29/41791 ,  H01L29/49 ,  H01L29/4958 ,  H01L29/66545 ,  H01L29/66795

Abstract: A range of lowest, low and regular threshold voltages are provided to three p-type devices and three n-type devices co-fabricated on a same substrate. For the p-type devices, the range is achieved for the lowest using an additional thick layer of a p-type work function metal in a gate structure and oxidizing it, the low Vt is achieved with the thick p-type work function metal alone, and the regular Vt is achieved with a thinner layer of the p-type work function metal. For the n-type devices, the lowest Vt is achieved by implanting tantalum nitride with arsenic, argon, silicon or germanium and not adding any of the additional p-type work function metal in the gate structure, the low Vt is achieved by not adding the additional p-type work function metal, and the regular Vt is achieved with a thinnest layer of the p-type work function metal.

Abstract translation: 三个p型器件和在同一衬底上共同制造的三个n型器件提供了一个最低，低和规则阈值电压范围。 对于p型器件，使用栅极结构中的p型功函数金属的附加厚层并对其进行氧化来实现最低的范围，低Vt由厚的p型功函数金属单独实现 ，并且通过p型功函数金属的较薄层实现常规Vt。 对于n型器件，最低的Vt是通过用砷，氩，硅或锗注入氮化钽而不是在栅极结构中添加任何附加的p型功函数金属来实现的，低Vt是通过不添加 额外的p型功函数金属，而常规Vt是用最薄层的p型功函金属实现的。

公开(公告)号：US20180069091A1

公开(公告)日：2018-03-08

申请号：US15256027

申请日：2016-09-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： George Robert MULFINGER ,  Dina H. TRIYOSO ,  Ryan SPORER

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/417 ,  H01L29/51 ,  H01L27/12 ,  H01L21/84

CPC classification number: H01L29/66545 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41783 ,  H01L29/517 ,  H01L29/66621 ,  H01L29/66628 ,  H01L29/786

Abstract: Methods for selectively thinning a silicon channel area under a gate electrode and resulting devices are disclosed. Embodiments include providing a SOI substrate including a Si-layer; providing a first dummy-gate electrode over a first gate-oxide between first spacers over a first channel area of the Si-layer and a second dummy-gate electrode over a second gate-oxide between second spacers over a second channel area of the Si-layer; forming a S/D region adjacent each spacer; forming an oxide over the S/D regions and the spacers; removing the dummy-gate electrodes creating first and second cavities between respective first and second spacers; forming a mask with an opening over the first cavity; removing the first gate-oxide; thinning the Si-layer under the first cavity, forming a recess in the Si-layer; forming a third gate-oxide on recess side and bottom surfaces; and filling the recess and the cavities with metal, forming first and second RMG electrodes.

公开(公告)号：US20160254145A1

公开(公告)日：2016-09-01

申请号：US14633246

申请日：2015-02-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Dina H. TRIYOSO ,  Wei Hua TONG ,  Haoran SHI ,  Jeremy Austin WAHL ,  Amy Lynn CHILD

IPC: H01L21/02 ,  H01L21/225 ,  H01L29/165 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L21/02236 ,  H01L21/02255 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/18 ,  H01L21/823807 ,  H01L21/84 ,  H01L29/165

Abstract: Methods of forming condensed first layer and semiconductor structures formed from the methods are provided. The methods include, for instance providing at least one layer disposed over a substrate structure of a semiconductor structure, wherein the substrate structure includes an upper silicon region; and performing at least one oxidation process of the semiconductor structure, the at least one oxidation process reducing a thickness of the upper region, wherein the performing facilitates diffusing to form a condensed layer over the substrate structure.

Abstract translation: 提供了由该方法形成的聚集的第一层和半导体结构的方法。 所述方法包括例如提供设置在半导体结构的衬底结构上的至少一层，其中衬底结构包括上硅区; 以及执行所述半导体结构的至少一个氧化工艺，所述至少一个氧化工艺减小所述上部区域的厚度，其中所述执行有助于扩散以在所述衬底结构上形成冷凝层。