公开(公告)号：US20210091189A1

公开(公告)日：2021-03-25

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi LIU ,  Vibhor JAIN ,  Judson R. HOLT ,  Herbert HO ,  Claude ORTOLLAND ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US20210091183A1

公开(公告)日：2021-03-25

申请号：US16830783

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/16 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

公开(公告)号：US20200219760A1

公开(公告)日：2020-07-09

申请号：US16241441

申请日：2019-01-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： Johnatan A. KANTAROVSKY ,  Siva P. ADUSUMILLI ,  Vibhor JAIN

IPC: H01L21/762 ,  H01L49/02 ,  H01L29/161 ,  H01L21/3065 ,  H01L21/02

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cavity structures under shallow trench isolation regions and methods of manufacture. The structure includes: one or more cavity structures provided in a substrate material and sealed with an epitaxial material; and a shallow trench isolation region directly above the one or more cavity structures in the substrate material.

公开(公告)号：US20180145160A1

公开(公告)日：2018-05-24

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. CAMILLO-CASTILLO ,  Vibhor JAIN ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L29/737 ,  H01L27/082 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8222 ,  H01L29/66 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H03F3/21

CPC classification number: H01L29/7375 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/324 ,  H01L21/8222 ,  H01L27/0823 ,  H01L27/0825 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/7371 ,  H03F3/21 ,  H03F2200/294

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US20210066194A1

公开(公告)日：2021-03-04

申请号：US17097432

申请日：2020-11-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. PEKARIK ,  Anthony K. STAMPER ,  Vibhor JAIN

IPC: H01L23/525 ,  H01L21/768 ,  H01L23/00 ,  H01L23/62

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to dual thickness fuse structures and methods of manufacture. The structure includes a continuous wiring structure on a single wiring level and composed of conductive material having a fuse portion and a thicker wiring structure.

公开(公告)号：US20200335612A1

公开(公告)日：2020-10-22

申请号：US16388500

申请日：2019-04-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Vibhor JAIN ,  Anthony K. STAMPER ,  Steven M. SHANK ,  John J. PEKARIK

IPC: H01L29/737 ,  H01L29/06

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor having an emitter base junction with a silicon-oxygen lattice interface and methods of manufacture. The device includes: a collector region buried in a substrate; shallow trench isolation regions, which isolate the collector region buried in the substrate; a base region on the substrate and over the collector region; an emitter region composed of a single crystalline of semiconductor material and located over with the base region; and an oxide interface at a junction of the emitter region and the base region.

公开(公告)号：US20190238105A1

公开(公告)日：2019-08-01

申请号：US15886475

申请日：2018-02-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anthony Kendall STAMPER ,  Vibhor JAIN ,  Humberto CAMPANELLA PINEDA ,  John Joseph PEKARIK

IPC: H03F3/21 ,  H01L21/304 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/762 ,  H01L27/02

Abstract: A method of forming a CMOS device and a GaN PA structure on a 100 Si substrate having a surface orientated in 111 direction and the resulting device are provided. Embodiments include forming a device with a protective layer over a portion of a Si substrate; forming a V-shaped groove in the Si substrate; forming a buffer layer, a GaN layer, an AlGaN layer and a passivation layer sequentially over the Si substrate; forming trenches through the passivation and the AlGaN layers; forming second trenches through the passivation layer; forming electrode structures over portions of the passivation layer and filling the first and second trenches; removing portions of the passivation layer, the AlGaN layer and the GaN layer outside of the V-shaped groove down to the buffer layer; forming a dielectric layer over the Si substrate; and forming vias through the dielectric layer down to electrode structures and the device.

公开(公告)号：US20180204761A1

公开(公告)日：2018-07-19

申请号：US15919744

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. FEILCHENFELD ,  Vibhor JAIN ,  Qizhi LIU

IPC: H01L21/762 ,  H01L29/868 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L27/08 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

公开(公告)号：US20210091180A1

公开(公告)日：2021-03-25

申请号：US16784813

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. PEKARIK ,  Vibhor JAIN ,  Herbert HO ,  Claude ORTOLLAND ,  Qizhi LIU

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.