公开(公告)号：US20180323066A1

公开(公告)日：2018-11-08

申请号：US15584121

申请日：2017-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Michel J. Abou-Khalil ,  Steven M. Shank ,  Alvin J. Joseph ,  Michael J. Zierak

IPC: H01L21/02 ,  H01L29/06 ,  H01L29/16 ,  H01L29/04 ,  H01L29/10 ,  H01L21/762 ,  H01L21/306

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/76224 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/1095 ,  H01L29/16

Abstract: Device structures for a field-effect transistor and methods of forming a device structure for a field-effect transistor. A trench isolation region is formed in a substrate, and surrounds a semiconductor body. An undercut cavity region is also formed in the substrate. The undercut cavity region extends laterally beneath the semiconductor body and defines a body pedestal as a section of the substrate that is arranged in vertical alignment with the semiconductor body.

公开(公告)号：US09893157B1

公开(公告)日：2018-02-13

申请号：US15401281

申请日：2017-01-09

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Max G. Levy ,  BethAnn Lawrence

IPC: H01L29/00 ,  H01L29/40 ,  H01L21/762 ,  H01L23/522 ,  H01L21/768 ,  H01L29/10 ,  H01L23/532 ,  H01L27/12 ,  H01L29/78

CPC classification number: H01L29/407 ,  H01L21/76283 ,  H01L21/76802 ,  H01L23/5226 ,  H01L23/53271 ,  H01L27/1207 ,  H01L29/107 ,  H01L29/1087 ,  H01L29/7824

Abstract: Structures that include contact trenches and isolation trenches, as well as methods for forming structures including contact trenches and isolation trenches. A contact trench is formed that extends through a device layer of a silicon-on-insulator (SOI) substrate to a buried oxide layer of the SOI substrate. An isolation trench is formed that extends through the device layer to the buried oxide layer. An electrical insulator is deposited that fills the contact trench and the first isolation trench. The electrical insulator is removed from the contact trench. After the electrical insulator is removed from the contact trench, an electrical conductor is formed in the contact trench. The electrical contact may be coupled with a doped region in a handle wafer of the SOI substrate.

公开(公告)号：US09595579B2

公开(公告)日：2017-03-14

申请号：US14712397

申请日：2015-05-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Max G. Levy ,  Richard A. Phelps ,  Santosh Sharma ,  Yun Shi ,  Michael J. Zierak

IPC: H01L29/78 ,  H01L29/06 ,  H01L21/762 ,  H01L29/10 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/0653 ,  H01L21/76232 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7846

Abstract: Various embodiments include structures for field effect transistors (FETs). In various embodiments, a structure for a FET includes: a deep n-type well; a shallow n-type well within the deep n-type well; and a shallow trench isolation (STI) region within the shallow n-type well, the STI region including: a first section having a first depth within the shallow n-type well as measured from an upper surface of the shallow n-type well, and a second section contacting and overlying the first section, the second section having a second depth within the shallow n-type well as measured from the upper surface of the shallow n-type well.

Abstract translation: 各种实施例包括用于场效应晶体管（FET）的结构。 在各种实施例中，用于FET的结构包括：深n型阱; 深n型井内浅层n型井; 以及在浅n型阱内的浅沟槽隔离（STI）区域，所述STI区域包括：从浅n型阱的上表面测量的，在浅n型阱内具有第一深度的第一部分， 以及与所述第一部分接触并覆盖的第二部分，所述第二部分具有从所述浅n型阱的上表面测量的所述浅n型阱内的第二深度。

公开(公告)号：US09799652B1

公开(公告)日：2017-10-24

申请号：US15635288

申请日：2017-06-28

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Theodore J. Letavic ,  Yun Shi ,  Santosh Sharma

IPC: H01L29/51 ,  H01L29/70 ,  H01L21/8222 ,  H01L21/331 ,  H01L27/092 ,  H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L21/265

CPC classification number: H01L27/092 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.

公开(公告)号：US09768028B1

公开(公告)日：2017-09-19

申请号：US15232873

申请日：2016-08-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. Feilchenfeld ,  Michael J. Zierak ,  Theodore J. Letavic ,  Yun Shi ,  Santosh Sharma

IPC: H01L21/76 ,  H01L21/311 ,  H01L21/302 ,  H01L21/266 ,  H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/225 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L21/2253 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/324 ,  H01L21/823814 ,  H01L29/0692 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7824 ,  H01L29/7835 ,  H01L29/78624

Abstract: Disclosed are methods that employ a mask with openings arranged in a pattern of elongated trenches and holes of varying widths to achieve a linearly graded conductivity level. These methods can be used to form a lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) with a drain drift region having an appropriate type conductivity at a level that increases essentially linearly from the body region to the drain region. Furthermore, these methods also provide for improve manufacturability in that multiple instances of this same pattern can be used during a single dopant implant process to implant a first dopant with a first type (e.g., N-type) conductivity into the drain drift regions of both first and second type LDMOSFETs (e.g., N and P-type LDMOSFETs, respectively). In this case, the drain drift region of a second type LDMOSFET can subsequently be uniformly counter-doped. Also disclosed are the resulting semiconductor structures.