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    Apparatus and method for vector s-parameter measurements
    3.
    发明授权
    Apparatus and method for vector s-parameter measurements 有权

    公开(公告)号：US09910124B2

    公开(公告)日：2018-03-06

    申请号：US15015176

    申请日：2016-02-04

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Adem G. Aydin ,  Hanyi Ding

    IPC: G01R27/04 ,  G01R35/00 ,  G01R27/28 ,  G01R27/02

    CPC classification number: G01R35/005 ,  G01R27/02 ,  G01R27/28

    Abstract: The disclosure relates to an apparatus and a method for vector scattering parameter (s-parameter) measurements, and more particularly, to an apparatus and a method for providing a simple, low cost solution for tests requiring vector s-parameter measurements. The apparatus includes a source which provides an input signal, a divider which splits the input signal to a reference signal and a testing signal, a phase shifter which shifts the reference signal by a first phase and outputs a phase shifted signal, a device under test (DUT) which shifts the testing signal by a second phase and outputs a DUT shifted signal, a combiner which combines the phase shifted signal and the DUT shifted signal into a combined signal, and a detector which detects a product of the phase shifted signal and the DUT shifted signal.

    Frequency-locked voltage regulated loop
    5.
    发明授权
    Frequency-locked voltage regulated loop 有权
    频率锁定电压调节回路

    公开(公告)号：US09503106B1

    公开(公告)日：2016-11-22

    申请号：US14966881

    申请日：2015-12-11

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hanyi Ding ,  Kai Di Feng

    IPC: H03L7/06 ,  H03L7/099 ,  H03L7/08 ,  H03L7/197

    CPC classification number: H03L7/06 ,  H03L7/00

    Abstract: An integrated circuit includes a frequency-locked voltage regulated loop that further includes a voltage controlled oscillator (VCO), a frequency divider that generates sequential timing signals based on a period of the VCO from a frequency divided VCO signal, a frequency-to-voltage converter (FVC) that converts the frequency divided VCO signal into an output voltage, FVCOUT, an internal reference voltage, and a voltage regulator that generates a control voltage, VCOIN, that is fed back to the VCO to lock a frequency of the VCO in the frequency-locked voltage regulated loop.

    Abstract translation: 集成电路包括频率锁定电压调节环路，其进一步包括压控振荡器（VCO），分频器，其基于来自频分压VCO信号的VCO的周期产生顺序定时信号，频率 - 电压 转换器（FVC），其将分频的VCO信号转换为输出电压，FVCOUT，内部参考电压和产生控制电压的电压调节器VCOIN，VCOIN反馈到VCO以锁定VCO的频率 锁频电压调节回路。

    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS
    6.
    发明申请
    BIPOLAR JUNCTION TRANSISTOR WITH MULTIPLE EMITTER FINGERS 有权
    具有多个发光指示器的双极接头晶体管

    公开(公告)号：US20160211345A1

    公开(公告)日：2016-07-21

    申请号：US14601655

    申请日：2015-01-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

    IPC: H01L29/66 ,  H01L29/73 ,  H01L29/08 ,  H01L21/306

    CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

    Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。

    Optical on-wafer probing with v-groove couplers
    7.
    发明授权
    Optical on-wafer probing with v-groove couplers 有权

    公开(公告)号：US10914897B2

    公开(公告)日：2021-02-09

    申请号：US16217838

    申请日：2018-12-12

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hanyi Ding ,  John Ferrario ,  John Joseph Cartier ,  Benjamin Michael Cadieux

    IPC: G02B6/36 ,  G02B6/30 ,  G02B6/35

    Abstract: A probe device is configured to insert optical fiber probes directly into a v-groove coupler on an optical integrated circuit (IC) device. The probe device may include a probe holder comprising with a slot. A fiber holder may insert into the slot. The fiber holder may comprise a body with a first portion and second portion disposed at an angle relative to one another so that the first portion is shorter than the second portion. The body may have a bottom with grooves disposed therein, the grooves having dimensions to receive part of an optical fiber probes therein. In use, the fiber holder can arrange the optical fiber probes to extend into the v-grooves of the v-groove coupler of an optical IC on a wafer. The device may incorporate an alignment mechanism that permits the fiber holder to move or “self-align” in response to contact between the optical fiber probes and structure of the v-groove coupler of an optical IC on a wafer.

    Inline measurement of through-silicon via depth
    9.
    发明授权
    Inline measurement of through-silicon via depth 有权

    公开(公告)号：US09865514B2

    公开(公告)日：2018-01-09

    申请号：US14643436

    申请日：2015-03-10

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Hanyi Ding ,  J. Edwin Hostetter ,  Ping-Chuan Wang ,  Kimball M. Watson

    IPC: H01L21/66 ,  H01L21/304

    CPC classification number: H01L22/26 ,  H01L21/304 ,  H01L22/14 ,  H01L22/34

    Abstract: A through-silicon via (TSV) capacitive test structure and method of determining TSV depth based on capacitance is disclosed. The TSV capacitive test structure is formed from a plurality of TSV bars that are evenly spaced. A first group of bars are electrically connected to form a first capacitor node, and a second group of bars is electrically connected to form a second capacitor node. The capacitance is measured, and a TSV depth is computed, prior to backside thinning. The computed TSV depth may then be fed to downstream grinding and/or polishing tools to control the backside thinning process such that the semiconductor wafer is thinned such that the backside is flush with the TSV.

    Bipolar junction transistor with multiple emitter fingers
    10.
    发明授权
    Bipolar junction transistor with multiple emitter fingers 有权
    具有多个发射极指的双极结晶体管

    公开(公告)号：US09543403B2

    公开(公告)日：2017-01-10

    申请号：US14601655

    申请日：2015-01-21

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Hanyi Ding ,  Vibhor Jain ,  Qizhi Liu

    IPC: H01L29/00 ,  H01L29/66 ,  H01L21/306 ,  H01L29/73 ,  H01L29/08

    CPC classification number: H01L29/66234 ,  H01L21/306 ,  H01L29/0688 ,  H01L29/0692 ,  H01L29/0804 ,  H01L29/0826 ,  H01L29/66242 ,  H01L29/66272 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7371

    Abstract: Device structures for a bipolar junction transistor and methods of fabricating a device structure for a bipolar junction transistor. A first semiconductor layer is formed on a substrate, and a second semiconductor layer is formed on the first semiconductor layer. The first semiconductor layer, the second semiconductor layer, and the substrate are etched to define first and second emitter fingers from the second semiconductor layer and trenches in the substrate that are laterally positioned between the first and second emitter fingers. The first semiconductor layer may function as a base layer in the device structure.

    Abstract translation: 用于双极结晶体管的器件结构以及制造用于双极结型晶体管的器件结构的方法。 在基板上形成第一半导体层，在第一半导体层上形成第二半导体层。 蚀刻第一半导体层，第二半导体层和衬底以限定来自第二半导体层的第一和第二发射极指状物以及横向位于第一和第二发射极指之间的衬底中的沟槽。 第一半导体层可以用作器件结构中的基层。

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