公开(公告)号：US20210091180A1

公开(公告)日：2021-03-25

申请号：US16784813

申请日：2020-02-07

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. PEKARIK ,  Vibhor JAIN ,  Herbert HO ,  Claude ORTOLLAND ,  Qizhi LIU

IPC: H01L29/08 ,  H01L29/66 ,  H01L29/737 ,  H01L29/165

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to virtual bulk in semiconductor on insulator technology and methods of manufacture. The structure includes a heterojunction bipolar transistor formed on a semiconductor on insulator (SOI) wafer with a doped sub-collector material in a buried insulator region under a semiconductor substrate of the SOI wafer.

公开(公告)号：US20170221888A1

公开(公告)日：2017-08-03

申请号：US15010189

申请日：2016-01-29

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Qizhi LIU ,  David HARAME ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/311 ,  H01L21/324 ,  H01L21/308 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.

公开(公告)号：US20180145160A1

公开(公告)日：2018-05-24

申请号：US15360295

申请日：2016-11-23

Applicant: GLOBALFOUNDRIES INC.

Inventor： Renata A. CAMILLO-CASTILLO ,  Vibhor JAIN ,  Qizhi LIU ,  Anthony K. STAMPER

IPC: H01L29/737 ,  H01L27/082 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/04 ,  H01L29/06 ,  H01L21/8222 ,  H01L29/66 ,  H01L21/02 ,  H01L21/268 ,  H01L21/324 ,  H03F3/21

CPC classification number: H01L29/7375 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02675 ,  H01L21/268 ,  H01L21/324 ,  H01L21/8222 ,  H01L27/0823 ,  H01L27/0825 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/66242 ,  H01L29/7371 ,  H03F3/21 ,  H03F2200/294

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to heterojunction bipolar transistor device integration schemes on a same wafer and methods of manufacture. The structure includes: a power amplifier (PA) device comprising a base, a collector and an emitter on a wafer; and a low-noise amplifier (LNA) device comprising a base, a collector and an emitter on the wafer, with the emitter having a same crystalline structure as the base.

公开(公告)号：US20190081138A1

公开(公告)日：2019-03-14

申请号：US15703220

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi LIU ,  Steven M. SHANK ,  John J. ELLIS-MONAGHAN ,  Anthony K. STAMPER

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/764 ,  H01L21/762 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

公开(公告)号：US20180204761A1

公开(公告)日：2018-07-19

申请号：US15919744

申请日：2018-03-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Natalie B. FEILCHENFELD ,  Vibhor JAIN ,  Qizhi LIU

IPC: H01L21/762 ,  H01L29/868 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L27/08 ,  H01L29/872 ,  H01L29/16 ,  H01L29/161

Abstract: Lateral PiN diodes and Schottky diodes with low parasitic capacitance and variable breakdown voltage structures and methods of manufacture are disclosed. The structure includes a diode with breakdown voltage determined by a dimension between p- and n-terminals formed in an i-region above a substrate.

公开(公告)号：US20210091189A1

公开(公告)日：2021-03-25

申请号：US16823005

申请日：2020-03-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi LIU ,  Vibhor JAIN ,  Judson R. HOLT ,  Herbert HO ,  Claude ORTOLLAND ,  John J. PEKARIK

IPC: H01L29/417 ,  H01L29/08 ,  H01L29/737 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a heterojunction bipolar transistor and methods of manufacture. The structure includes: a sub-collector region; a collector region in electrical connection to the sub-collector region; an emitter located adjacent to the collector region and comprising emitter material, recessed sidewalls on the emitter material and an extension region extending at an upper portion of the emitter material above the recessed sidewalls; and an extrinsic base separated from the emitter by the recessed sidewalls.

公开(公告)号：US20210091183A1

公开(公告)日：2021-03-25

申请号：US16830783

申请日：2020-03-26

Applicant: GLOBALFOUNDRIES INC.

Inventor： Judson R. HOLT ,  Vibhor JAIN ,  Qizhi LIU ,  John J. PEKARIK

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/737 ,  H01L29/16 ,  H01L29/66

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to heterojunction bipolar transistors and methods of manufacture. The structure includes a collector region composed of semiconductor material; at least one marker layer over the collector region; a layer of doped semiconductor material which forms an extrinsic base and which is located above the at least one marker layer; a cavity formed in the layer of doped semiconductor material and extending at least to the at least one marker layer; an epitaxial intrinsic base layer of doped material located within the cavity; and an emitter material over the epitaxial intrinsic base layer and within an opening formed by sidewall spacer structures.

公开(公告)号：US20170256541A1

公开(公告)日：2017-09-07

申请号：US15599751

申请日：2017-05-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Qizhi LIU ,  David HARAME ,  Renata Camillo-Castillo

IPC: H01L27/088 ,  H01L21/308 ,  H01L21/311 ,  H01L21/324 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L21/324 ,  H01L21/823821 ,  H01L21/823892 ,  H01L29/66803

Abstract: A method of making a semiconductor structure is provided including providing a plurality of fins on a semiconductor substrate; depositing a layer containing silicon dioxide on the plurality of fins and on a surface of the semiconductor substrate; depositing a photoresist layer on one or more but less than all of the plurality of fins; etching the layer of silicon dioxide off of one or more of the plurality of fins on which the photoresist layer had not been deposited; stripping the photoresist layer; depositing a layer of pure boron on one or more of the plurality of fins on which a photoresist had not been deposited; and depositing a silicon nitride liner step on the plurality of fins. A partial semiconductor device fabricated by said method is also provided.