公开(公告)号：US09064086B2

公开(公告)日：2015-06-23

申请号：US14525833

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract translation: 一种方法包括在计算装置中接收用于集成电路装置的设计布局文件。 设计布局文件指定多个特征的尺寸。 将设计布局文件分解为多个彩色布局文件，每个彩色布局文件在多重图案化处理中表示特定的掩模版。 每个彩色布局文件在计算设备中分别重新定位，以产生多个重定向彩色布局文件。 重新定位每个彩色布局文件包括基于第一多个特征和相邻特征之间的间隔来增加第一多个特征的尺寸。 重新定位的布局文件被组合以生成组合的布局文件。 组合布局文件中的特征在计算装置中重新定位，以基于第二多个特征和相邻特征之间的间隔来增加第二多个特征的尺寸。

公开(公告)号：US08869075B2

公开(公告)日：2014-10-21

申请号：US13717816

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidambaram Kallingal ,  Marc Tarabbia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract translation: 提供了清洁/分辨光刻热点的方法（例如，在半导体设计的模拟阶段期间）。 通常，将在光刻图案或轮廓的第一多边形（具有第一颜色）中识别热点。 一旦确定了热点，将识别靠近热点的位置（例如，具有第一颜色的第一多边形的另一部分或具有第一颜色的第二多边形），以放置针迹标记。 一旦识别出位置，将在该位置放置一个针迹标记。 然后，将针迹标记位置的颜色改变为第二颜色，并且可以进一步处理所得到的平版印刷图案以清洁/解析热点。

公开(公告)号：US20140235055A1

公开(公告)日：2014-08-21

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US20140253902A1

公开(公告)日：2014-09-11

申请号：US14286285

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Norman S. Chen ,  Jian Liu

IPC: G03F7/20

CPC classification number: G03F7/70 ,  G03F1/68 ,  G03F1/70 ,  G03F1/76

Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.

Abstract translation: 本文公开的一种说明性方法涉及识别由至少一个孔型特征组成的总体目标图案，将总体目标图案分解为至少第一子目标图案和第二子目标图案，其中第一子目标图案 并且所述第二子目标图案各自包括至少一个公共孔型特征，产生与所述第一子目标图案相对应的第一组掩模数据信息，以及生成与所述第二子目标图形对应的第二组掩模数据信息， 目标模式。

公开(公告)号：US20140223390A1

公开(公告)日：2014-08-07

申请号：US13760571

申请日：2013-02-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuyang Sun ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract translation: 一种方法包括在计算装置中接收用于集成电路装置的设计布局文件。 设计布局文件指定多个特征的尺寸。 将设计布局文件分解为多个彩色布局文件，每个彩色布局文件在多重图案化处理中表示特定的掩模版。 每个彩色布局文件在计算设备中分别重新定位，以产生多个重定向彩色布局文件。 重新定位每个彩色布局文件包括基于第一多个特征和相邻特征之间的间隔来增加第一多个特征的尺寸。 重新定位的布局文件被组合以生成组合的布局文件。 组合布局文件中的特征在计算装置中被重新定位，以基于第二多个特征和相邻特征之间的间隔来增加第二多个特征的尺寸。

公开(公告)号：US09171735B2

公开(公告)日：2015-10-27

申请号：US13767993

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Sohan Mehta ,  Norman Chen ,  Yuyang Sun ,  Matthew Herrick ,  Shyam Pal ,  Jeong Soo Kim

IPC: H01L21/308 ,  G03F7/00

CPC classification number: H01L21/308 ,  G03F7/0035 ,  H01L21/0337 ,  H01L21/3086

Abstract: Methods are provided for fabricating semiconductor integrated circuits including isolated trench features. In one embodiment, a method includes providing a semiconductor substrate with an overlying process layer. A trench pattern to be etched into the process layer is determined and that trench pattern is decomposed into first and second patterns, the second pattern including an isolated trench. First and second lithographic masks are formed to implement the first and second patterns, the second mask implementing the second pattern, the isolated trench, and a plurality of density balancer patterns symmetrically positioned with respect to the isolated trench. A first resist layer is patterned with the first lithographic mask and the process layer is etched with the first resist layer. A second resist layer is patterned with the second lithographic mask and the process layer is etched with the second resist layer to implement the required trench pattern in the process layer.

Abstract translation: 提供了用于制造包括隔离沟槽特征的半导体集成电路的方法。 在一个实施例中，一种方法包括向半导体衬底提供上覆工艺层。 确定要蚀刻到处理层中的沟槽图案，并且沟槽图案被分解成第一和第二图案，第二图案包括隔离的沟槽。 形成第一和第二光刻掩模以实现第一和第二图案，实现第二图案的第二掩模，隔离沟槽以及相对于隔离沟槽对称定位的多个密度平衡器图案。 利用第一光刻掩模对第一抗蚀剂层进行图案化，并且用第一抗蚀剂层蚀刻处理层。 用第二光刻掩模对第二抗蚀剂层进行构图，并且用第二抗蚀剂层蚀刻处理层以在处理层中实现所需的沟槽图案。

公开(公告)号：US08993224B2

公开(公告)日：2015-03-31

申请号：US14286285

申请日：2014-05-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Norman S. Chen ,  Jian Liu

IPC: G03F7/00 ,  G03F7/20 ,  G03F1/68 ,  G03F1/76

CPC classification number: G03F7/70 ,  G03F1/68 ,  G03F1/70 ,  G03F1/76

Abstract: One illustrative method disclosed herein involves identifying an overall target pattern comprised of at least one hole-type feature, decomposing the overall target pattern into at least a first sub-target pattern and a second sub-target pattern, wherein the first sub-target pattern and the second sub-target pattern each comprise at least one common hole-type feature, generating a first set of mask data information corresponding to the first sub-target pattern, and generating a second set of mask data information corresponding to the second sub-target pattern.

Abstract translation: 本文公开的一种说明性方法涉及识别由至少一个孔型特征组成的总体目标图案，将总体目标图案分解为至少第一子目标图案和第二子目标图案，其中第一子目标图案 并且所述第二子目标图案各自包括至少一个公共孔型特征，产生与所述第一子目标图案相对应的第一组掩模数据信息，以及生成与所述第二子目标图形对应的第二组掩模数据信息， 目标模式。

公开(公告)号：US08910094B2

公开(公告)日：2014-12-09

申请号：US13760571

申请日：2013-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yuyang Sun ,  Chidam Kallingal ,  Norman Chen

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5068 ,  G06F2217/06

Abstract: A method includes receiving a design layout file for an integrated circuit device in a computing apparatus. The design layout file specifies dimensions of a plurality of features. The design layout file is decomposed to a plurality of colored layout files, each colored layout file representing a particular reticle in a multiple patterning process. Each of the colored layout files is retargeted separately in the computing apparatus to generate a plurality of retargeted colored layout files. Retargeting each of the colored layout files includes increasing dimensions of a first plurality of features based on spacings between the first plurality of features and adjacent features. The retargeted layout files are combined to generate a combined layout file. Features in the combined layout file are retargeted in the computing apparatus to increase dimensions of a second plurality of features based on spacings between the second plurality of features and adjacent features.

Abstract translation: 一种方法包括在计算装置中接收用于集成电路装置的设计布局文件。 设计布局文件指定多个特征的尺寸。 将设计布局文件分解为多个彩色布局文件，每个彩色布局文件在多重图案化处理中表示特定的掩模版。 每个彩色布局文件在计算设备中分别重新定位，以产生多个重定向彩色布局文件。 重新定位每个彩色布局文件包括基于第一多个特征和相邻特征之间的间隔来增加第一多个特征的尺寸。 重新定位的布局文件被组合以生成组合的布局文件。 组合布局文件中的特征在计算装置中被重新定位，以基于第二多个特征和相邻特征之间的间隔来增加第二多个特征的尺寸。

公开(公告)号：US20140173533A1

公开(公告)日：2014-06-19

申请号：US13717816

申请日：2012-12-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Yuyang Sun ,  Chidambaram Kallingal ,  Marc Tarabbia

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F2217/12 ,  Y02P90/265

Abstract: Approaches for cleaning/resolving lithographic hotspots (e.g., during a simulation phase of semiconductor design) are provided. Typically, a hotspot will be identified in a first polygon (having a first color) of a lithographic pattern or contour. Once a hotspot has been identified, a location (e.g., another portion of the first polygon or in a second polygon of the lithographic pattern having the first color) proximate the hotspot will be identified to place a stitch marker. Once the location has been identified, a stitch marker will be placed at that location. Then, a color of the stitch marked location will be changed to a second color, and the resulting lithographic pattern can be further processed to clean/resolve the hotspot.

Abstract translation: 提供了清洁/分辨光刻热点的方法（例如，在半导体设计的模拟阶段期间）。 通常，将在光刻图案或轮廓的第一多边形（具有第一颜色）中识别热点。 一旦确定了热点，将识别靠近热点的位置（例如，具有第一颜色的第一多边形的另一部分或具有第一颜色的第二多边形），以放置针迹标记。 一旦识别出位置，将在该位置放置一个针迹标记。 然后，将针迹标记位置的颜色改变为第二颜色，并且可以进一步处理所得到的平版印刷图案以清洁/解析热点。