公开(公告)号：US09431294B2

公开(公告)日：2016-08-30

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US20150087149A1

公开(公告)日：2015-03-26

申请号：US14037774

申请日：2013-09-26

Applicant: Globalfoundries, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。

公开(公告)号：US10566231B2

公开(公告)日：2020-02-18

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768 ,  H01L23/532

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US20190333805A1

公开(公告)日：2019-10-31

申请号：US15966032

申请日：2018-04-30

Applicant: GLOBALFOUNDRIES INC.

Inventor： Martin J. O'Toole ,  Christopher J. Penny ,  Jae O. Choo ,  Adam L. da Silva ,  Craig Child ,  Terry A. Spooner ,  Hsueh-Chung Chen ,  Brendan O'Brien ,  Keith P. Donegan

IPC: H01L21/768

Abstract: Methods of forming an interconnect of an IC are disclosed. The methods include forming a first interlayer dielectric (ILD) layer and a second ILD layer with an ILD etch stop layer (ESL) therebetween. The ILD ESL has an etch rate that is at least five times slower than the first and second ILD layers, and may include, for example, aluminum oxynitride. A dual damascene (DD) hard mask is used to form a wire trench opening in the second ILD layer and a via opening in the first ILD layer, creating a via-wire opening. Due to the slower etch rate, the ILD ESL defines the via opening in the first ILD layer as a chamferless via opening. A unitary via-wire conductive structure coupled to the conductive structure in the via-wire opening can be formed from the via-wire opening.

公开(公告)号：US20160190207A1

公开(公告)日：2016-06-30

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L27/22 ,  H01L43/08 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

Abstract translation: 提供了包括用于磁阻随机存取存储器（MRAM）的磁性隧道结（MTJ）和用于制造这种集成电路的方法的集成电路。 在一个示例中，制造集成电路的方法包括在金属互连上形成下电极。 金属互连设置在半导体衬底之上并且与基本上垂直于半导体衬底的法线对准。 下电极包括导电金属插头。 在与正常轴对准的下电极上形成MTJ堆叠。

公开(公告)号：US09691971B2

公开(公告)日：2017-06-27

申请号：US14749165

申请日：2015-06-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Seowoo Nam ,  Ming He ,  Craig Child ,  Hyun-Jin Cho

IPC: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L27/22

CPC classification number: H01L43/12 ,  H01L27/228 ,  H01L43/02 ,  H01L43/08 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits that include a magnetic tunnel junction (MTJ) for a magnetoresistive random-access memory (MRAM) and methods for fabricating such integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a lower electrode on a metal interconnect. The metal interconnect is disposed above a semiconductor substrate and is aligned with a normal axis that is substantially perpendicular to the semiconductor substrate. The lower electrode includes a conductive metal plug. A MTJ stack is formed on the lower electrode aligned with the normal axis.

公开(公告)号：US20160372413A1

公开(公告)日：2016-12-22

申请号：US14741636

申请日：2015-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Anbu Selvam Mahalingam ,  Ashwini Chandrashekar ,  Craig Child

IPC: H01L23/528 ,  H01L21/311 ,  H01L23/522 ,  H01L21/02 ,  H01L23/532 ,  H01L21/3205 ,  H01L21/768

CPC classification number: H01L23/53295 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76832 ,  H01L23/5226 ,  H01L23/53238

Abstract: One method includes, among other things, forming a bi-layer etch stop layer above a conductive contact comprised of titanium nitride, the bi-layer etch stop layer consisting of an upper second layer that is made of aluminum nitride, forming a patterned etch mask comprised of a layer of titanium nitride above a second layer of insulating material, with the bi-layer etch stop layer in position above the conductive contact, performing an etching process through the patterned etch mask to define a cavity in the second layer of insulating material, performing a second etching process to remove at least the layer of titanium nitride of the patterned etch mask, forming an opening in the bi-layer etch stop layer so as to thereby expose a portion of the conductive contact and forming a conductive structure in the cavity that is conductively coupled to the exposed portion of the conductive contact.

Abstract translation: 一种方法包括在包括氮化钛的导电接触层之上形成双层蚀刻停止层，双层蚀刻停止层由由氮化铝制成的上部第二层组成，形成图案化的蚀刻掩模 包括在第二绝缘材料层上方的氮化钛层，双层蚀刻停止层位于导电接触点上方的位置，通过图案化的蚀刻掩模执行蚀刻工艺，以在第二绝缘材料层中限定空腔 ，执行第二蚀刻工艺以去除图案化蚀刻掩模的至少所述氮化钛层，在双层蚀刻停止层中形成开口，从而暴露导电接触的一部分并在其中形成导电结构 导电地耦合到导电触点的暴露部分的腔。

公开(公告)号：US20160118292A1

公开(公告)日：2016-04-28

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US09165770B2

公开(公告)日：2015-10-20

申请号：US14037774

申请日：2013-09-26

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Seowoo Nam ,  Craig Child

IPC: C03C15/00 ,  C03C25/68 ,  C23F1/00 ,  B44C1/22 ,  H01L21/033

CPC classification number: H01L21/0338 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139

Abstract: Methods for fabricating integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes forming a mask overlying a material to be etched by forming first hard mask segments overlying the material to be etched, forming sacrificial mandrels overlying the material to be etched and around each hard mask segment, forming second hard mask segments overlying the semiconductor substrate and adjacent each sacrificial mandrel, and removing the sacrificial mandrels to form first gaps surrounding each first hard mask segment, wherein each first gap is bounded by a respective first hard mask segment and an adjacent second hard mask segment. The method includes etching the material to be etched through the mask.

Abstract translation: 提供了制造集成电路的方法。 在一个实施例中，制造集成电路的方法包括：通过形成覆盖待蚀刻材料的第一硬掩模段形成覆盖待蚀刻材料的掩模，形成覆盖待蚀刻材料和围绕每个硬掩模段的牺牲心轴， 形成覆盖所述半导体衬底并邻近所述牺牲心轴的第二硬掩模段，以及去除所述牺牲心轴以形成围绕每个第一硬掩模段的第一间隙，其中每个第一间隙由相应的第一硬掩模段和相邻的第二硬掩模 分割。 该方法包括通过掩模蚀刻待蚀刻的材料。