公开(公告)号：US20150357120A1

公开(公告)日：2015-12-10

申请号：US14298040

申请日：2014-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick Alan Augur ,  Jason Eugene Stephens

IPC: H01G4/30 ,  H01G4/005 ,  H01G4/06

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/01 ,  H01G4/06 ,  H01G4/232 ,  H01G4/385 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract translation: 电容器结构包括第一金属层，第一金属层包括在第一多个水平间隔的高压导电线之间水平定位的第一多个水平间隔的中性导电线。 电容器结构还包括第二金属层，第二金属层包括位于第二多个水平间隔的高压导电线之间水平定位的第二多个水平间隔的中性导电线。 所述电容器结构还包括位于所述第一金属层的垂直下方且位于所述第二金属层的上方的第三金属层，所述第三金属层包括第三多个水平间隔的中性导电线，其水平位于第一多个水平间隔的低电压 导线。 第一组多个低压线路垂直地定位在第一和第二多个中性线之间。

公开(公告)号：US10090258B1

公开(公告)日：2018-10-02

申请号：US15713843

申请日：2017-09-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kevin Boyd ,  Robert Fox ,  Jeannine Trewhella ,  Roderick Alan Augur ,  Nicholas A. Polomoff

IPC: H01L23/00 ,  H01L23/31 ,  H01L21/768 ,  H01L23/535

Abstract: One illustrative crack-stop structure disclosed herein may include a first crack-stop metallization layer comprising a first metal line layer that has a plurality of openings formed therein and a second crack-stop metallization layer positioned above and adjacent the first crack-stop metallization layer, wherein the second crack-stop metallization layer has a second metal line layer and a via layer, and wherein the via layer comprises a plurality of vias having a portion that extends at least partially into the openings in the first metal line layer of the first crack-stop metallization layer so as to thereby form a stepped, non-planar interface between the first metal line layer of the first crack-stop metallization layer and the via layer of the second crack-stop metallization layer.

公开(公告)号：US09576735B2

公开(公告)日：2017-02-21

申请号：US14298040

申请日：2014-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Roderick Alan Augur ,  Jason Eugene Stephens

IPC: H01L49/02 ,  H01L23/522 ,  H01G4/30 ,  H01G4/005 ,  H01G4/06 ,  H01G4/38 ,  H01G4/01 ,  H01G4/232

CPC classification number: H01G4/30 ,  H01G4/005 ,  H01G4/01 ,  H01G4/06 ,  H01G4/232 ,  H01G4/385 ,  H01L23/5223 ,  H01L28/88 ,  H01L28/91 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A capacitor structure includes a first metal layer including a first plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a second metal layer including a second plurality of horizontally-spaced neutral conductive lines positioned horizontally between a second plurality of horizontally-spaced high voltage conductive lines. The capacitor structure further includes a third metal layer positioned vertically below the first metal layer and above the second metal layer, the third metal layer including a third plurality of horizontally-spaced neutral conductive lines positioned horizontally between a first plurality of horizontally-spaced low voltage conductive lines. The first plurality of low voltage lines are positioned vertically between the first and second plurality of neutral lines.

Abstract translation: 电容器结构包括第一金属层，第一金属层包括在第一多个水平间隔的高压导电线之间水平定位的第一多个水平间隔的中性导电线。 电容器结构还包括第二金属层，第二金属层包括位于第二多个水平间隔的高压导电线之间水平定位的第二多个水平间隔的中性导电线。 所述电容器结构还包括位于所述第一金属层的垂直下方且位于所述第二金属层的上方的第三金属层，所述第三金属层包括第三多个水平间隔的中性导电线，其水平位于第一多个水平间隔的低电压 导线。 第一组多个低压线路垂直地定位在第一和第二多个中性线之间。

公开(公告)号：US20160118292A1

公开(公告)日：2016-04-28

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528 ,  H01L21/02

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。

公开(公告)号：US10181420B2

公开(公告)日：2019-01-15

申请号：US15425478

申请日：2017-02-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jason Eugene Stephens ,  David Michael Permana ,  Guillaume Bouche ,  Andy Wei ,  Mark Zaleski ,  Anbu Selvam K M Mahalingam ,  Craig Michael Child, Jr. ,  Roderick Alan Augur ,  Shyam Pal ,  Linus Jang ,  Xiang Hu ,  Akshey Sehgal

IPC: H01L21/768 ,  H01L21/311 ,  H01L21/027 ,  H01L23/522 ,  H01L23/528

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices with chamfer-less via multi-patterning are disclosed. One method includes, for instance: obtaining an intermediate semiconductor device; performing a trench etch into a portion of the intermediate semiconductor device to form a trench pattern; depositing an etching stack; performing at least one via patterning process; and forming at least one via opening into a portion of the intermediate semiconductor device. An intermediate semiconductor device is also disclosed.

公开(公告)号：US09431294B2

公开(公告)日：2016-08-30

申请号：US14525796

申请日：2014-10-28

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ming He ,  Errol Todd Ryan ,  Roderick Alan Augur ,  Craig Child ,  Larry Zhao

IPC: H01L21/4763 ,  H01L21/76 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/7682 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76849 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Integrated circuits and methods for producing the same are provided. A method for producing an integrated circuit includes forming an interconnect trench in a dielectric layer, and forming a conformal barrier layer overlying the dielectric layer and within the interconnect trench. A barrier spacer is formed by removing the conformal barrier layer from an interconnect trench bottom, and an interconnect is formed within the interconnect trench after forming the barrier spacer. An air gap trench is formed in the dielectric layer adjacent to the barrier spacer, and a top cap is formed overlying the interconnect and the air gap trench, where the top cap bridges the air gap trench to produce an air gap in the air gap trench.

Abstract translation: 提供了集成电路及其制造方法。 一种用于制造集成电路的方法包括在电介质层中形成互连沟槽，以及形成覆盖在介电层上和互连沟槽内的共形阻挡层。 通过从互连沟槽底部去除共形阻挡层而形成阻挡间隔物，并且在形成阻挡间隔物之后在互连沟槽内形成互连。 在邻近阻挡间隔物的电介质层中形成气隙沟槽，并且顶盖形成在互连和气隙沟槽上方，顶盖与气隙沟槽连接，以在气隙沟槽中产生气隙 。