公开(公告)号：US20150200111A1

公开(公告)日：2015-07-16

申请号：US14153120

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Sruthi Muralidharan ,  Zhenyu Hu ,  Qi Zhang ,  Ja-Hyung Han ,  Dinesh Koli ,  Zhuangfei Chen

IPC: H01L21/321 ,  H01L21/02 ,  H01L21/265

CPC classification number: H01L21/32115 ,  H01L21/28035 ,  H01L21/28123 ,  H01L21/32137 ,  H01L29/66545 ,  H01L29/66795

Abstract: Embodiments of the present invention provide improved methods for fabrication of finFETs. During finFET fabrication, a film, such as amorphous silicon, is deposited on a semiconductor substrate which has regions with fins and regions without fins. A fill layer is deposited on the film and planarized to form a flush surface. A recess or etch process is used to form a planar surface with all portions of the fill layer removed. A finishing process such as a gas cluster ion beam process may be used to further smooth the substrate surface. This results in a film having a very uniform thickness across the structure (e.g. a semiconductor wafer), resulting in improved within-wafer (WiW) uniformity and improved within-chip (WiC) uniformity.

Abstract translation: 本发明的实施例提供了用于制造finFET的改进方法。 在finFET制造期间，诸如非晶硅的膜沉积在半导体衬底上，该半导体衬底具有鳍片和不具有鳍片的区域。 填充层沉积在膜上并且被平坦化以形成齐平表面。 使用凹陷或蚀刻工艺来形成平坦表面，其中填充层的所有部分被去除。 可以使用诸如气体簇离子束工艺的精加工工艺来进一步平滑衬底表面。 这导致在结构（例如半导体晶片）上具有非常均匀的厚度的膜，导致晶片内（WiW）的均匀性提高和芯片内（WiC）均匀性提高。

公开(公告)号：US10056458B2

公开(公告)日：2018-08-21

申请号：US14993537

申请日：2016-01-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Chang Ho Maeng ,  Andy Wei ,  Anthony Ozzello ,  Bharat Krishnan ,  Guillaume Bouche ,  Haifeng Sheng ,  Haigou Huang ,  Huang Liu ,  Huy M. Cao ,  Ja-Hyung Han ,  SangWoo Lim ,  Kenneth A. Bates ,  Shyam Pal ,  Xintuo Dai ,  Jinping Liu

IPC: H01L21/3205 ,  H01L29/40 ,  H01L29/423 ,  H01L21/02 ,  H01L21/28 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/02126 ,  H01L21/02282 ,  H01L21/28229 ,  H01L21/76828 ,  H01L21/76837 ,  H01L21/76897 ,  H01L29/41791 ,  H01L29/4232 ,  H01L29/78

Abstract: Methods of MOL S/D contact patterning of RMG devices without gouging of the Rx area or replacement of the dielectric are provided. Embodiments include forming a SOG layer around a RMG structure, the RMG structure having a contact etch stop layer and a gate cap layer; forming a lithography stack over the SOG and gate cap layers; patterning first and second TS openings through the lithography stack down to the SOG layer; removing a portion of the SOG layer through the first and second TS openings, the removing selective to the contact etch stop layer; converting the SOG layer to a SiO2 layer; forming a metal layer over the SiO2 layer; and planarizing the metal and SiO2 layers down to the gate cap layer.