公开(公告)号：US20150235906A1

公开(公告)日：2015-08-20

申请号：US14705732

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Johannes von Kluge ,  Berthold Reimer

IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/423 ,  H01L21/285 ,  H01L29/51

CPC classification number: H01L21/823857 ,  H01L21/265 ,  H01L21/28 ,  H01L21/28035 ,  H01L21/285 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31155 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518

Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

Abstract translation: 本文公开了在制造集成电路中蚀刻电介质材料的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成的栅电极结构上形成第一电介质材料层。 栅电极结构包括水平顶表面和邻近水平顶表面的侧壁垂直表面。 该方法还包括在第一介电材料的层上形成第二电介质材料层。 第一电介质材料与第二电介质材料不同。 此外，该方法包括向第二材料施加蚀刻剂，该蚀刻剂从侧壁垂直表面完全去除第二材料，同时仅从第二材料部分地从水平顶部表面移除，同时基本上不去除第一介电材料层 。

公开(公告)号：US20150024578A1

公开(公告)日：2015-01-22

申请号：US13945144

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Johannes von Kluge ,  Berthold Reimer

IPC: H01L21/306 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L21/306 ,  H01L21/265 ,  H01L21/28 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/31155

Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

公开(公告)号：US09537006B2

公开(公告)日：2017-01-03

申请号：US14933557

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes von Kluge

IPC: H03K19/094 ,  H01L29/78 ,  G05F3/02 ,  H01L21/66 ,  H01L27/088 ,  H01L29/66 ,  H03K19/20 ,  H01L49/02 ,  H01L29/8605 ,  H03K19/017 ,  H01L27/092 ,  G05F3/26 ,  H01L21/8238

CPC classification number: H01L29/7842 ,  G05F3/02 ,  G05F3/262 ,  H01L21/823807 ,  H01L22/30 ,  H01L27/088 ,  H01L27/092 ,  H01L28/20 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/8605 ,  H03K19/017 ,  H03K19/20

Abstract: An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a first layer of a first stress-creating material, the first stress-creating material providing a stress that is variable in response to a signal acting on the first stress-creating material, wherein the first layer of the first stress-creating material is arranged to provide a first variable stress in the first channel region of the first transistor, the first variable stress being variable in response to a first signal acting on the first stress-creating material. The integrated circuit also includes a second transistor having a second source region, a second drain region, a second channel region, and a second gate electrode.

Abstract translation: 集成电路包括具有第一源区，第一漏区，第一沟道区，第一栅极和第一应力产生材料的第一层的第一晶体管，所述第一应力产生材料提供应力， 响应于作用在第一应力产生材料上的信号而变化，其中第一应力产生材料的第一层被布置成在第一晶体管的第一沟道区域中提供第一可变应力，第一可变应力为 响应于作用在第一应力产生材料上的第一信号而变化。 集成电路还包括具有第二源极区域，第二漏极区域，第二沟道区域和第二栅极电极的第二晶体管。

公开(公告)号：US20160056288A1

公开(公告)日：2016-02-25

申请号：US14933557

申请日：2015-11-05

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes von Kluge

IPC: H01L29/78 ,  G05F3/26 ,  H03K19/20 ,  H01L27/092

CPC classification number: H01L29/7842 ,  G05F3/02 ,  G05F3/262 ,  H01L21/823807 ,  H01L22/30 ,  H01L27/088 ,  H01L27/092 ,  H01L28/20 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/8605 ,  H03K19/017 ,  H03K19/20

Abstract: An integrated circuit includes a first transistor having a first source region, a first drain region, a first channel region, a first gate electrode, and a first layer of a first stress-creating material, the first stress-creating material providing a stress that is variable in response to a signal acting on the first stress-creating material, wherein the first layer of the first stress-creating material is arranged to provide a first variable stress in the first channel region of the first transistor, the first variable stress being variable in response to a first signal acting on the first stress-creating material. The integrated circuit also includes a second transistor having a second source region, a second drain region, a second channel region, and a second gate electrode.

Abstract translation: 集成电路包括具有第一源区，第一漏区，第一沟道区，第一栅极和第一应力产生材料的第一层的第一晶体管，所述第一应力产生材料提供应力， 响应于作用在第一应力产生材料上的信号而变化，其中第一应力产生材料的第一层被布置成在第一晶体管的第一沟道区域中提供第一可变应力，第一可变应力为 响应于作用在第一应力产生材料上的第一信号而变化。 集成电路还包括具有第二源极区域，第二漏极区域，第二沟道区域和第二栅极电极的第二晶体管。

公开(公告)号：US20140113455A1

公开(公告)日：2014-04-24

申请号：US13655844

申请日：2012-10-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

IPC: H01L21/306

CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

公开(公告)号：US20140232433A1

公开(公告)日：2014-08-21

申请号：US13768275

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES INC.

Inventor： Johannes von Kluge

IPC: H01L27/088 ,  H03K19/20 ,  G05F3/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L29/7842 ,  G05F3/02 ,  G05F3/262 ,  H01L21/823807 ,  H01L22/30 ,  H01L27/088 ,  H01L27/092 ,  H01L28/20 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/8605 ,  H03K19/017 ,  H03K19/20

Abstract: A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors.

Abstract translation: 晶体管包括源极区，漏极区，沟道区，栅电极和应力产生材料层。 应力产生材料提供响应于作用在应力产生材料上的信号而变化的应力。 应力产生材料层被布置成在至少沟道区域中产生应力。 至少在通道区域中提供的应力响应于作用在应力产生材料上的信号而变化。 提供响应于作用在应力产生材料上的信号而变化的应力的应力产生材料层也可用于除了晶体管之外的电路元件，例如电阻器。

公开(公告)号：US08716136B1

公开(公告)日：2014-05-06

申请号：US13655844

申请日：2012-10-19

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

IPC: H01L21/311

CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

公开(公告)号：US09209174B2

公开(公告)日：2015-12-08

申请号：US13768275

申请日：2013-02-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Johannes von Kluge

IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  G05F3/02 ,  H01L21/66 ,  H03K19/20 ,  H01L49/02 ,  H01L29/8605 ,  H03K19/017 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L29/7842 ,  G05F3/02 ,  G05F3/262 ,  H01L21/823807 ,  H01L22/30 ,  H01L27/088 ,  H01L27/092 ,  H01L28/20 ,  H01L29/66477 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/78 ,  H01L29/7833 ,  H01L29/8605 ,  H03K19/017 ,  H03K19/20

Abstract: A transistor includes a source region, a drain region, a channel region, a gate electrode and a layer of a stress-creating material. The stress-creating material provides a stress that is variable in response to a signal acting on the stress-creating material. The layer of stress-creating material is arranged to provide a stress in at least the channel region. The stress provided in at least the channel region is variable in response to the signal acting on the stress-creating material. Layers of stress-creating material providing a stress that is variable in response to a signal acting on the stress-creating material may also be used in circuit elements other than transistors, for example, resistors.

Abstract translation: 晶体管包括源极区，漏极区，沟道区，栅电极和应力产生材料层。 应力产生材料提供响应于作用在应力产生材料上的信号而变化的应力。 应力产生材料层被布置成在至少沟道区域中产生应力。 至少在通道区域中提供的应力响应于作用在应力产生材料上的信号而变化。 提供响应于作用在应力产生材料上的信号而变化的应力的应力产生材料层也可用于除了晶体管之外的电路元件，例如电阻器。

公开(公告)号：US09054041B2

公开(公告)日：2015-06-09

申请号：US13945144

申请日：2013-07-18

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Johannes von Kluge ,  Berthold Reimer

IPC: H01L21/306 ,  H01L21/265 ,  H01L21/28

CPC classification number: H01L21/306 ,  H01L21/265 ,  H01L21/28 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/31155

Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

Abstract translation: 本文公开了在制造集成电路中蚀刻电介质材料的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成的栅电极结构上形成第一电介质材料层。 栅电极结构包括水平顶表面和邻近水平顶表面的侧壁垂直表面。 该方法还包括在第一介电材料的层上形成第二电介质材料层。 第一电介质材料与第二电介质材料不同。 此外，该方法包括向第二材料施加蚀刻剂，该蚀刻剂从侧壁垂直表面完全去除第二材料，同时仅从第二材料部分地从水平顶部表面移除，同时基本上不去除第一介电材料层 。