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    FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL
    1.
    发明申请
    FIELD-EFFECT TRANSISTORS WITH A GROWN SILICON-GERMANIUM CHANNEL 审中-公开

    公开(公告)号：US20200051808A1

    公开(公告)日：2020-02-13

    申请号：US16102066

    申请日：2018-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Carsten Metze ,  Berthold Reimer ,  Simeon Morvan

    IPC: H01L21/02 ,  H01L27/12 ,  H01L21/762 ,  H01L21/321 ,  H01L21/324 ,  H01L21/8234

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first channel region containing a first semiconductor material and a second channel region containing a second semiconductor material are formed over a buried insulating layer of a silicon-on-insulator substrate. A first gate electrode of a first field-effect transistor is formed over the first channel region. A second gate electrode of a second field-effect transistor is formed over the second channel region. The first semiconductor material of the first channel region has a first germanium concentration. The second semiconductor material of the second channel region has a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region.

    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS
    2.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR DEVICE BY PERFORMING A WET ACID ETCHING PROCESS WHILE PREVENTING OR REDUCING LOSS OF ACTIVE AREA AND/OR ISOLATION REGIONS 有权
    通过在预防或减少活动区域和/或分离区域的损失的同时进行湿酸蚀刻工艺来形成半导体器件的方法

    公开(公告)号：US20140227869A1

    公开(公告)日：2014-08-14

    申请号：US14172135

    申请日：2014-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

    IPC: H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

    Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE
    3.
    发明申请
    METHOD OF FORMING A SEMICONDUCTOR STRUCTURE INCLUDING A WET ETCH PROCESS FOR REMOVING SILICON NITRIDE 有权
    形成除去硅酸盐浸渍过程的半导体结构的方法

    公开(公告)号：US20140113455A1

    公开(公告)日：2014-04-24

    申请号：US13655844

    申请日：2012-10-19

    Applicant: GLOBALFOUNDRIES INC.

    Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

    IPC: H01L21/306

    CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

    Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

    Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

    Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions
    6.
    发明授权
    Methods of forming a semiconductor device by performing a wet acid etching process while preventing or reducing loss of active area and/or isolation regions 有权
    通过执行湿酸蚀刻工艺同时防止或减少有源区和/或隔离区的损失来形成半导体器件的方法

    公开(公告)号：US08815674B1

    公开(公告)日：2014-08-26

    申请号：US14172135

    申请日：2014-02-04

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Markus Lenski ,  Bastian Haussdoerfer ,  Ardechir Pakfar

    IPC: H01L21/8238 ,  H01L21/28 ,  H01L29/40

    CPC classification number: H01L29/401 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/78

    Abstract: One method disclosed includes forming a sidewall spacer proximate a gate structure, forming a sacrificial layer of material above a protective cap layer, the sidewall spacer and a substrate, forming a sacrificial protection layer above the sacrificial layer, reducing a thickness of the sacrificial protection layer such that its upper surface is positioned at a level that is below the upper surface of the protective cap layer, performing a first etching process to remove a portion of the sacrificial layer and thereby expose the protective cap layer for further processing, performing a wet acid etching process that includes diluted HF acid in the etch chemistry to remove the protective cap layer and performing at least one process operation to remove at least one of the reduced-thickness sacrificial protection layer or the sacrificial layer from above the surface of the substrate.

    Abstract translation: 所公开的一种方法包括在栅极结构附近形成侧壁间隔物，在保护盖层之上形成牺牲层材料，侧壁间隔物和衬底，在牺牲层上形成牺牲保护层，减小牺牲保护层的厚度 使得其上表面位于保护盖层的上表面下方的水平处，执行第一蚀刻工艺以去除牺牲层的一部分，从而露出保护盖层用于进一步处理，执行湿酸 蚀刻工艺，其在蚀刻化学中包括稀释的HF酸以去除保护盖层，并执行至少一个工艺操作以从衬底的表面上方去除至少一个减薄的牺牲保护层或牺牲层。

    Method of forming a semiconductor structure including a wet etch process for removing silicon nitride
    7.
    发明授权
    Method of forming a semiconductor structure including a wet etch process for removing silicon nitride 有权
    形成包括用于去除氮化硅的湿蚀刻工艺的半导体结构的方法

    公开(公告)号：US08716136B1

    公开(公告)日：2014-05-06

    申请号：US13655844

    申请日：2012-10-19

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Berthold Reimer ,  Johannes von Kluge ,  Sven Beyer

    IPC: H01L21/311

    CPC classification number: H01L29/6656 ,  H01L21/0206 ,  H01L21/28052 ,  H01L21/31111 ,  H01L29/665 ,  H01L29/7833

    Abstract: A method disclosed herein includes providing a semiconductor structure comprising a transistor, the transistor comprising a gate electrode and a silicon nitride sidewall spacer formed at the gate electrode. A wet etch process is performed. The wet etch process removes at least a portion of the silicon nitride sidewall spacer. The wet etch process comprises applying an etchant comprising at least one of hydrofluoric acid and phosphoric acid.

    Abstract translation: 本文公开的方法包括提供包括晶体管的半导体结构，所述晶体管包括形成在栅极处的栅电极和氮化硅侧壁间隔物。 执行湿蚀刻工艺。 湿蚀刻工艺去除氮化硅侧壁间隔物的至少一部分。 湿蚀刻工艺包括施加包含氢氟酸和磷酸中的至少一种的蚀刻剂。

    Methods for etching dielectric materials in the fabrication of integrated circuits
    8.
    发明授权
    Methods for etching dielectric materials in the fabrication of integrated circuits 有权
    在集成电路制造中蚀刻电介质材料的方法

    公开(公告)号：US09054041B2

    公开(公告)日：2015-06-09

    申请号：US13945144

    申请日：2013-07-18

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Johannes von Kluge ,  Berthold Reimer

    IPC: H01L21/306 ,  H01L21/265 ,  H01L21/28

    CPC classification number: H01L21/306 ,  H01L21/265 ,  H01L21/28 ,  H01L21/28035 ,  H01L21/31111 ,  H01L21/31155

    Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

    Abstract translation: 本文公开了在制造集成电路中蚀刻电介质材料的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成的栅电极结构上形成第一电介质材料层。 栅电极结构包括水平顶表面和邻近水平顶表面的侧壁垂直表面。 该方法还包括在第一介电材料的层上形成第二电介质材料层。 第一电介质材料与第二电介质材料不同。 此外，该方法包括向第二材料施加蚀刻剂，该蚀刻剂从侧壁垂直表面完全去除第二材料，同时仅从第二材料部分地从水平顶部表面移除，同时基本上不去除第一介电材料层 。

    Field-effect transistors with a grown silicon-germanium channel
    9.
    发明授权
    Field-effect transistors with a grown silicon-germanium channel 有权

    公开(公告)号：US10559593B1

    公开(公告)日：2020-02-11

    申请号：US16102066

    申请日：2018-08-13

    Applicant: GLOBALFOUNDRIES Inc.

    Inventor： Carsten Metze ,  Berthold Reimer ,  Simeon Morvan

    IPC: H01L27/12 ,  H01L21/02 ,  H01L21/8234 ,  H01L21/321 ,  H01L21/324 ,  H01L21/762

    Abstract: Structures for a field-effect transistor and methods of forming a structure for a field-effect transistor. A first channel region containing a first semiconductor material and a second channel region containing a second semiconductor material are formed over a buried insulating layer of a silicon-on-insulator substrate. A first gate electrode of a first field-effect transistor is formed over the first channel region. A second gate electrode of a second field-effect transistor is formed over the second channel region. The first semiconductor material of the first channel region has a first germanium concentration. The second semiconductor material of the second channel region has a second germanium concentration that is greater than the first germanium concentration in the first semiconductor material of the first channel region.

    METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS
    10.
    发明申请
    METHODS FOR ETCHING DIELECTRIC MATERIALS IN THE FABRICATION OF INTEGRATED CIRCUITS 审中-公开
    在集成电路制造中蚀刻电介质材料的方法

    公开(公告)号：US20150235906A1

    公开(公告)日：2015-08-20

    申请号：US14705732

    申请日：2015-05-06

    Applicant: GLOBALFOUNDRIES, Inc.

    Inventor： Johannes von Kluge ,  Berthold Reimer

    IPC: H01L21/8238 ,  H01L21/306 ,  H01L29/423 ,  H01L21/285 ,  H01L29/51

    CPC classification number: H01L21/823857 ,  H01L21/265 ,  H01L21/28 ,  H01L21/28035 ,  H01L21/285 ,  H01L21/306 ,  H01L21/30604 ,  H01L21/31111 ,  H01L21/31155 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518

    Abstract: Methods for etching dielectric materials in the fabrication of integrated circuits are disclosed herein. In one exemplary embodiment, a method for fabricating an integrated circuit includes forming a layer of a first dielectric material over a gate electrode structure formed on a semiconductor substrate. The gate electrode structure includes a horizontal top surface and sidewall vertical surfaces adjacent to the horizontal top surface. The method further includes forming a layer of a second dielectric material over the layer of the first dielectric material. The first dielectric material is different than the second dielectric material. Still further, the method includes applying an etchant to the second material that fully removes the second material from the sidewall vertical surfaces while only partially removing the second material from the horizontal top surface and while substantially not removing any of the layer of the first dielectric material.

    Abstract translation: 本文公开了在制造集成电路中蚀刻电介质材料的方法。 在一个示例性实施例中，一种用于制造集成电路的方法包括在半导体衬底上形成的栅电极结构上形成第一电介质材料层。 栅电极结构包括水平顶表面和邻近水平顶表面的侧壁垂直表面。 该方法还包括在第一介电材料的层上形成第二电介质材料层。 第一电介质材料与第二电介质材料不同。 此外，该方法包括向第二材料施加蚀刻剂，该蚀刻剂从侧壁垂直表面完全去除第二材料，同时仅从第二材料部分地从水平顶部表面移除，同时基本上不去除第一介电材料层 。

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