公开(公告)号：US20160155737A1

公开(公告)日：2016-06-02

申请号：US14838375

申请日：2015-08-28

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Handoko LINEWIH ,  Ming LI ,  Sevashanmugam MARIMUTHU ,  Ronghua YU

IPC分类号： H01L27/02 ,  H01L27/06 ,  H01L49/02 ,  H01L21/762 ,  H01L21/8234 ,  H01L21/768 ,  H02H9/04 ,  H01L29/10

CPC分类号： H01L21/76224 ,  H01L27/0274 ,  H01L27/0629 ,  H01L29/1095 ,  H02H9/04

摘要： Devices and methods of forming an integrated circuit (IC) that offer protection against ESD in high voltage (HV) circuit applications are disclosed. A device includes N ones of a field effect transistor (FET) stacked in series to provide an N-level stack, where N is an integer greater than 1. A first pad of the device is coupled to a first FET and a second pad is coupled to an Nth FET. The device also includes a stacked/distributed RC control circuit configured to cause a short circuit between the first pad and the second pad in response to an ESD event. During the ESD event, the RC control circuit is configured to concurrently provide sufficient voltage to control the N ones of the FET by turning them on using parasitic conduction to cause the short circuit.

摘要翻译： 公开了在高电压（HV）电路应用中形成提供ESD保护的集成电路（IC）的装置和方法。 一种器件包括串联堆叠的N个场效应晶体管（FET），以提供N级堆栈，其中N是大于1的整数。器件的第一焊盘耦合到第一FET，第二焊盘是 耦合到第N个FET。 该装置还包括被配置为响应于ESD事件而在第一焊盘和第二焊盘之间引起短路的堆叠/分布式RC控制电路。 在ESD事件期间，RC控制电路被配置成同时提供足够的电压以通过使用寄生导通来使它们接通以导致短路来控制FET的N个电压。

公开(公告)号：US20210320203A1

公开(公告)日：2021-10-14

申请号：US16847750

申请日：2020-04-14

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Ming LI ,  Sivaramasubramaniam RAMASUBRAMANIAM ,  Dong Hyun SHIN ,  Di WU ,  Yunpeng XU ,  Chenji ZOU ,  Jeoung Mo KOO

IPC分类号： H01L29/78 ,  H01L29/417 ,  H01L29/66 ,  H01L21/762 ,  H01L21/02 ,  H01L21/311

摘要： According to various embodiments, a transistor device may include a substrate. The transistor device may further include a drain terminal and a source terminal formed in the substrate, and a gate terminal formed over the substrate. The transistor device may further include an insulator structure arranged between the drain terminal and the source terminal, and at least partially under the gate terminal. The insulator structure may include an oxide member and a trench isolation region. The oxide member may be at least partially formed over the trench isolation region.

公开(公告)号：US20190189779A1

公开(公告)日：2019-06-20

申请号：US15842899

申请日：2017-12-15

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Ming LI ,  Jeoung Mo KOO ,  Raj Verma PURAKH

IPC分类号： H01L29/66 ,  H01L21/762 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/08 ,  H01L21/265 ,  H01L21/02 ,  H01L29/78 ,  H01L29/06 ,  H01L21/28 ,  H01L29/36

CPC分类号： H01L29/66681 ,  H01L21/02238 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28035 ,  H01L21/31053 ,  H01L21/32137 ,  H01L21/76224 ,  H01L21/76229 ,  H01L22/26 ,  H01L27/092 ,  H01L29/063 ,  H01L29/0649 ,  H01L29/0865 ,  H01L29/0882 ,  H01L29/1095 ,  H01L29/36 ,  H01L29/402 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/4916 ,  H01L29/7816

摘要： A method for forming a high voltage device is disclosed. The method comprises providing a substrate defined with a high voltage device region. A device well is formed to encompass the high voltage device region. A drift region is formed within the device well. A body well is formed within the device well adjacent to the drift region. A variable thickness gate dielectric is formed on the substrate. Forming the variable thickness gate dielectric comprises patterned a sacrificial polysilicon layer and oxidizing the patterned sacrificial polysilicon layer to define a thick gate oxide having sloped sidewalls. A gate electrode is formed on the variable thickness gate dielectric, wherein the gate electrode partially overlaps the thick gate oxide. A first and a second source/drain (S/D) region is formed adjacent to first and second sides of the variable thickness gate dielectric.

公开(公告)号：US20160322262A1

公开(公告)日：2016-11-03

申请号：US14698883

申请日：2015-04-29

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Ming LI ,  Jeoung Mo KOO ,  Purakh Raj VERMA

IPC分类号： H01L21/8234 ,  H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/306 ,  H01L21/321 ,  H01L29/40 ,  H01L29/66 ,  H01L21/762 ,  H01L29/10

CPC分类号： H01L21/76224 ,  H01L21/26586 ,  H01L21/761 ,  H01L21/76229 ,  H01L21/823878 ,  H01L21/823892 ,  H01L27/092 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7835

摘要： Devices and methods for forming a device are presented. A substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate. An epitaxial layer is formed over the buried layer. Deep trench isolation (DTI) regions which extend from top surface of the epitaxial layer to a portion of the substrate are formed. The DTI regions isolate different buried regions defined in the buried layer. Sinker tap regions which at least partially surround sides of the DTI regions and extend from the epitaxial layer into a portion of the buried layer are formed. The sinker tap region connects sinker taps to the buried layer. Shallow trench isolation (STI) regions are formed in the epitaxial layer. At least one transistor is formed on the epitaxial layer,

摘要翻译： 提出了用于形成装置的装置和方法。 提供了具有轻掺杂的第一极性类型掺杂剂的衬底。 在衬底的顶部形成具有重掺杂的第二极性类型掺杂剂的掩埋层。 在掩埋层上形成外延层。 形成从外延层的顶表面延伸到衬底的一部分的深沟槽隔离（DTI）区域。 DTI区域隔离在埋层中限定的不同掩埋区域。 形成至少部分地围绕DTI区域的侧面并从外延层延伸到掩埋层的一部分中的沉淀器抽头区域。 沉降片分接区将沉降片分接头连接到埋层。 在外延层中形成浅沟槽隔离（STI）区域。 在外延层上形成至少一个晶体管，

公开(公告)号：US20160163583A1

公开(公告)日：2016-06-09

申请号：US14958873

申请日：2015-12-03

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Kun LIU ,  Francis BENISTANT ,  Ming LI ,  Namchil MUN ,  Shiang Yang ONG ,  Purakh Raj VERMA

IPC分类号： H01L21/762 ,  H01L29/78 ,  H01L21/311 ,  H01L29/06 ,  H01L21/763 ,  H01L21/321

CPC分类号： H01L21/76229 ,  H01L21/76283 ,  H01L21/763 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0922 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/66681 ,  H01L29/78 ,  H01L29/7816

摘要： Semiconductor device isolation and method of forming thereof are presented. A base substrate with lightly doped first polarity type dopants is provided. A buried layer with heavily doped second polarity type dopants is formed in a top portion of the substrate while an epitaxial layer is formed over the buried layer. First and second type deep trench isolation (DTI) structures which extend from surface of the epitaxial layer to a portion of the base substrate are formed to isolate different device regions defined in the substrate. The first and second type DTI structures have different width dimensions. Shallow trench isolation (STI) regions are formed in the epitaxial layer and at least one transistor is formed on the epitaxial layer. The first and second type DTI structures effectively isolate the transistor from other device regions and enhances the breakdown voltage.

摘要翻译： 介绍了半导体器件隔离及其形成方法。 提供了具有轻掺杂的第一极性类型掺杂剂的基底。 在衬底的顶部形成具有重掺杂的第二极性类型掺杂剂的掩埋层，同时在掩埋层上形成外延层。 形成从外延层的表面延伸到基底基板的一部分的第一和第二类型深沟槽隔离（DTI）结构以隔离限定在基板中的不同器件区域。 第一和第二类型DTI结构具有不同的宽度尺寸。 在外延层中形成浅沟槽隔离（STI）区域，并且在外延层上形成至少一个晶体管。 第一和第二类型DTI结构有效地将晶体管与其他器件区域隔离并增强击穿电压。

公开(公告)号：US20130187218A1

公开(公告)日：2013-07-25

申请号：US13669409

申请日：2012-11-05

申请人： GLOBALFOUNDRIES SINGAPORE PTE. LTD.

发明人： Da-Wei LAI ,  Ming LI ,  Jeoung Mo KOO ,  Purakh Raj VERMA

IPC分类号： H01L29/78

CPC分类号： H01L29/78 ,  H01L27/027 ,  H01L29/0623 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/456 ,  H01L29/4933 ,  H01L29/7816 ,  H01L29/7835

摘要： A device which includes a substrate defined with a device region having an ESD protection circuit is disclosed. The ESD protection circuit has a transistor. The transistor includes a gate having first and second sides. A first diffusion region is disposed adjacent to the first side of the gate and a second diffusion region is disposed in the device region displaced away from the second side of the gate. The first and second diffusion regions include dopants of a first polarity type. A drift isolation region is disposed between the gate and the second diffusion region. A first device well encompasses the device region and a second device well is disposed within the first device well. A drain well having dopants of the first polarity type is disposed under the second diffusion region and within the first device well.

摘要翻译： 公开了一种包括由具有ESD保护电路的器件区限定的衬底的器件。 ESD保护电路具有晶体管。 晶体管包括具有第一和第二侧面的栅极。 第一扩散区域邻近栅极的第一侧设置，并且第二扩散区域设置在远离栅极的第二侧移位的器件区域中。 第一和第二扩散区域包括第一极性类型的掺杂剂。 漂移隔离区域设置在栅极和第二扩散区域之间。 第一装置阱包围装置区域，第二装置井设置在第一装置井内。 具有第一极性类型的掺杂剂的漏极阱设置在第二扩散区域的下方和第一器件阱内。

公开(公告)号：US20140264556A1

公开(公告)日：2014-09-18

申请号：US13967372

申请日：2013-08-15

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Da-Wei LAI ,  Ming LI

IPC分类号： H01L27/02

CPC分类号： H01L29/78 ,  H01L27/0277 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region disposed adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well encompasses the device region and a second device well disposed within the first device well. The second device well encompasses the first diffusion region and at least a part of the gate. The device also includes a third well which is disposed within the second device well and a drain well which encompasses the second diffusion region and extends below the gate.

摘要翻译： 提出了具有由器件区域限定的衬底的器件。 器件区域包括具有晶体管的ESD保护电路。 晶体管包括具有第一和第二侧的栅极，邻近栅极的第一侧设置的第一扩散区域和离开栅极第二侧的第二扩散区域。 所述装置包括井的第一装置，所述装置区域以及设置在所述第一装置井内的第二装置。 第二装置阱包围第一扩散区域和栅极的至少一部分。 该装置还包括设置在第二装置阱内的第三阱和包围第二扩散区并在栅极下方延伸的排水井。

公开(公告)号：US20140084366A1

公开(公告)日：2014-03-27

申请号：US13967370

申请日：2013-08-15

申请人： GLOBALFOUNDRIES Singapore Pte. Ltd.

发明人： Da-Wei LAI ,  Ming LI

IPC分类号： H01L29/78

CPC分类号： H01L29/7816 ,  H01L27/027 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/665 ,  H01L29/7835 ,  H01L29/861

摘要： A device having a substrate defined with a device region is presented. The device region includes an ESD protection circuit having a transistor. The transistor includes a gate having first and second sides, a first diffusion region adjacent to the first side of the gate and a second diffusion region displaced away from the second side of the gate. The device includes a first device well which encompasses the device region and a second device well disposed within the first device well. The device further includes a drift well which encompasses the second diffusion region of which edges of the drift well do not extend below the gate and is away from a channel region, and a drain well which is disposed under the second diffusion region and extends below the gate.

摘要翻译： 提出了具有由器件区域限定的衬底的器件。 器件区域包括具有晶体管的ESD保护电路。 晶体管包括具有第一和第二侧的栅极，与栅极的第一侧相邻的第一扩散区域和离开栅极的第二侧移位的第二扩散区域。 该装置包括包围装置区域的第一装置井和位于第一装置井内的第二装置。 该装置还包括漂移阱，其包围漂移井的边缘不延伸到栅极下方并且远离沟道区域的第二扩散区域，以及设置在第二扩散区域下方并延伸到第二扩散区域下方的漏极阱 门。