公开(公告)号：US20210141610A1

公开(公告)日：2021-05-13

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: G06F7/58 ,  H04L9/32 ,  H01L29/772 ,  H01L27/07 ,  H01L21/8234

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US11907685B2

公开(公告)日：2024-02-20

申请号：US16677717

申请日：2019-11-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Judson R. Holt ,  Julien Frougier ,  Ryan W. Sporer ,  George R. Mulfinger ,  Daniel Jaeger

IPC: H04L9/32 ,  G06F7/58 ,  H04L9/08 ,  G06F21/00 ,  G06F21/73 ,  G06F21/72 ,  G06F21/76 ,  H01L21/02 ,  H01L27/088

CPC classification number: G06F7/588 ,  G06F21/00 ,  G06F21/72 ,  G06F21/73 ,  G06F21/76 ,  H01L21/02233 ,  H04L9/0866 ,  H04L9/3278 ,  H01L27/088 ,  H04L2209/12

Abstract: Disclosed is a structure for implementing a Physically Unclonable Function (PUF)-based random number generator and a method for forming the structure. The structure includes same-type, same-design devices in a semiconductor layer. While values of a performance parameter exhibited by some devices (i.e., first devices) are within a range established based on the design, values of the same performance parameter exhibited by other devices (i.e., second devices) is outside that range. A random distribution of the first and second devices is achieved by including randomly patterned dopant implant regions in the semiconductor layer. Each first device is separated from the dopant implant regions such that its performance parameter value is within the range and each second device has a junction with dopant implant region(s) such that its performance parameter value is outside the range or vice versa. A random number generator can be operably connected to the devices to generate a PUF-based random number.

公开(公告)号：US20230112377A1

公开(公告)日：2023-04-13

申请号：US17496296

申请日：2021-10-07

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Kaustubh Shanbhag ,  Eric S. Kozarsky ,  George R. Mulfinger ,  Jianwei Peng

IPC: H01L27/12 ,  H01L21/84

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to semiconductor devices with a shared common backside well and methods of manufacture. The structure includes: adjacent gate structures over a semiconductor substrate; a common well in the semiconductor substrate under the adjacent gate structures; a deep trench isolation structure extending through the common well between the adjacent gate structures; and a shared diffusion region between the adjacent gate structures.

公开(公告)号：US12176351B2

公开(公告)日：2024-12-24

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L21/84 ,  H01L27/146 ,  H01L29/06

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20230047046A1

公开(公告)日：2023-02-16

申请号：US17973618

申请日：2022-10-26

Applicant: GlobalFoundries U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/146 ,  H01L29/06 ,  H01L21/84

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US20230038887A1

公开(公告)日：2023-02-09

申请号：US17394770

申请日：2021-08-05

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Ryan Sporer ,  George R. Mulfinger ,  Yusheng Bian

IPC: H01L27/12 ,  H01L21/84 ,  H01L29/06 ,  H01L21/762 ,  H01L27/146

Abstract: Structures for a photonics chip that include a fully-depleted silicon-on-insulator field-effect transistor and related methods. A first device region of a substrate includes a first device layer, a first portion of a second device layer, and a buried insulator layer separating the first device layer from the first portion of the second device layer. A second device region of the substrate includes a second portion of the second device layer. The first device layer, which has a thickness in a range of about 4 to about 20 nanometers, transitions in elevation to the second portion of the second device layer with a step height equal to a sum of the thicknesses of the first device layer and the buried insulator layer. A field-effect transistor includes a gate electrode on the top surface of the first device layer. An optical component includes the second portion of the second device layer.

公开(公告)号：US11101364B2

公开(公告)日：2021-08-24

申请号：US16296769

申请日：2019-03-08

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： George R. Mulfinger ,  Hong Yu ,  Man Gu ,  Jianwei Peng ,  Michael Aquilino

IPC: H01L29/66 ,  H01L29/78 ,  H01L21/311

Abstract: Structures for a field-effect transistor and methods of forming a field-effect transistor. A gate structure of the field-effect transistor is arranged over an active region comprised of a semiconductor material. A first sidewall spacer is arranged adjacent to the gate structure. A second sidewall spacer includes a section arranged between the first sidewall spacer and the active region. The first sidewall spacer is composed of a low-k dielectric material.

公开(公告)号：US20210226044A1

公开(公告)日：2021-07-22

申请号：US16745833

申请日：2020-01-17

Applicant: GLOBALFOUNDRIES U.S. Inc.

Inventor： Alexander Derrickson ,  Edmund K. Banghart ,  Alexander Martin ,  Ryan Sporer ,  Jagar Singh ,  Katherina Babich ,  George R. Mulfinger

IPC: H01L29/737 ,  H01L29/08 ,  H01L29/10 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02 ,  H01L21/324

Abstract: Structures for a heterojunction bipolar transistor and methods of forming a structure for a heterojunction bipolar transistor. A first portion of a first semiconductor layer defines an emitter, a first portion of a second semiconductor layer defines a collector, and a base includes respective second portions of the first and second semiconductor layers that are laterally positioned between the first portion of the first semiconductor layer and the first portion of the second semiconductor layer. The first portion of the first semiconductor layer has a first thickness, and the first portion of the second semiconductor layer has a second thickness that is greater than the first thickness. The first portion and the second portion of the first semiconductor layer adjoin at a first junction having the first thickness. The first portion and the second portion of the second semiconductor layer adjoin at a second junction having the second thickness.

公开(公告)号：US11031484B2

公开(公告)日：2021-06-08

申请号：US16456268

申请日：2019-06-28

Applicant: GLOBALFOUNDRIES U.S. INC.

Inventor： George R. Mulfinger ,  Judson R. Holt ,  Mark Raymond

IPC: H01L29/66 ,  H01L27/12 ,  H01L21/84 ,  H01L29/08

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to differential silicide structures and methods of manufacture. The structure includes: a substrate; a gate structure comprising a silicided gate region; and source and drain regions adjacent to the gate structure and comprising S/D silicided regions having a differential thickness compared to the silicided gate region.

公开(公告)号：US20230352348A1

公开(公告)日：2023-11-02

申请号：US17732601

申请日：2022-04-29

Applicant: GlobalFoundries U.S. Inc.

Inventor： George R. Mulfinger ,  Md Nasir Uddin Bhuyian ,  Shesh Mani Pandey ,  Adam S. Rosenfeld ,  Selina A. Mala

IPC: H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/08 ,  H01L29/66

CPC classification number: H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66553 ,  H01L29/6656

Abstract: Disclosed are a semiconductor structure and method of forming the structure. The structure has a semiconductor layer. A gate structure is located on the semiconductor layer. The gate structure has a sidewall spacer having a first section on the semiconductor layer and positioned laterally adjacent to the gate structure and further having a second section above and wider than the first section and positioned laterally adjacent the gate structure. A source/drain region is on the semiconductor layer and positioned laterally adjacent to the first section and the second section of the sidewall spacer.