公开(公告)号：US20230267831A1

公开(公告)日：2023-08-24

申请号：US17679368

申请日：2022-02-24

Applicant: GM Global Technology Operations LLC

Inventor： SHIGE WANG ,  Wei Tong ,  Shuqing Zeng ,  Xiaofeng Frank Song ,  Sourav Dey ,  Praveen Choudhury

IPC: G08G1/017 ,  G07C5/00 ,  G07C5/02 ,  G08G1/01

CPC classification number: G08G1/017 ,  G07C5/008 ,  G07C5/02 ,  G08G1/0112

Abstract: An automobile vehicle continuous validation system includes a backend collecting data from a vehicle fleet and wirelessly communicating with the vehicle fleet. The backend is in wireless communication with at least one client. A vehicle module is provided on-board individual ones of multiple automobile vehicles of the vehicle fleet and performing an on-board vehicle validation analysis. A fleet-based validation module provided either at the backend or cloud based manages data defining a configuration of and a capability of the multiple automobile vehicles of the vehicle fleet. A validation manager generates validation tasks based on a user's definition or a desired production of the validation tasks of the validation analysis and a fleet vehicle availability. A client-side module remote from the multiple automobile vehicles of the vehicle fleet has interface items applied by the at least one client seeking to perform the validation analysis.

公开(公告)号：US20150331829A1

公开(公告)日：2015-11-19

申请号：US14278797

申请日：2014-05-15

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  CHANG LIU ,  TRENTON W. HAINES ,  JAMES T. KURNIK

IPC: G06F13/42 ,  G06F13/16

CPC classification number: G06F9/52 ,  G06F13/1642 ,  G06F13/1673 ,  G06F13/4243

Abstract: A system and method for accessing coherent data on a controller. The system and method include a first buffer and a second buffer that each may be read from or written to and an indicator that indicates which of the first or the second buffer is read from while the other of the first or second buffers is written to. The system and method also include a read synchronization protocol that allows the coherent data to be read from the buffer that the indicator indicates is the read buffer and a write synchronization protocol that allows the coherent data to be written to the buffer that the indicator indicates is the write buffer.

Abstract translation: 一种用于在控制器上访问相干数据的系统和方法。 该系统和方法包括第一缓冲器和第二缓冲器，每个缓冲器和第二缓冲器每个可以被读取或写入，以及指示器，其指示从第一或第二缓冲器中的另一个被写入时读取第一或第二缓冲器中的哪一个。 该系统和方法还包括读取同步协议，其允许从缓冲器读取指示符指示为读取缓冲器的相干数据，以及允许将相干数据写入指示符指示的缓冲器的写入同步协议 写缓冲区。

公开(公告)号：US20230264709A1

公开(公告)日：2023-08-24

申请号：US17679388

申请日：2022-02-24

Applicant: GM Global Technology Operations LLC

Inventor： SHIGE WANG ,  Wei Tong ,  Donald K. Grimm

IPC: B60W60/00 ,  B60W40/09

CPC classification number: B60W60/001 ,  B60W40/09 ,  B60W2540/30 ,  B60W2420/42 ,  B60W2555/20

Abstract: An on-demand, feature focused data collection system of an automobile vehicle includes at least one data collection device provided with an automobile vehicle. A data collection unit receives data from the at least one data collection device in response to a data collection request submitted by a user. A data scene group combines portions of the data received by the data collection unit and stored in the data collection unit of the automobile vehicle or at a remote server. A control logic device receives the data collection request and activates collection of the data. The control logic device includes: a data collection strategy which differs if different types of the data are available; a reference algorithm loaded or deployed; a storage capacity allocated for the data; and a storage policy employed to save the data.

公开(公告)号：US20170078878A1

公开(公告)日：2017-03-16

申请号：US14853266

申请日：2015-09-14

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  STEPHEN G. LUSKO

IPC: H04W12/06 ,  H04L29/08 ,  H04L12/58

CPC classification number: H04W12/06 ,  H04L12/40013 ,  H04L51/26 ,  H04L63/08 ,  H04L67/12 ,  H04L2012/40215

Abstract: A secure messaging communication system. A communication bus communicates messages between transmitting nodes. A secure hardware engine of a controller authenticates messages from requesting entities. A processor of the controller initially receives messages from the requesting entities. The processor includes a message request queue prioritizing received messages. The processor communicates a prioritized message from the request queue and associated authentication information to the secure hardware engine. The secure hardware engine authenticates the messages in response to receiving the prioritized messages and associated authentication information from the processor. The secure hardware engine communicates the authenticated messages to the processor for storage in a results queue.

Abstract translation: 安全消息通信系统。 通信总线在发送节点之间传送消息。 控制器的安全硬件引擎对来自请求实体的消息进行认证。 控制器的处理器最初从请求实体接收消息。 处理器包括对接收的消息进行优先级排列的消息请求队列。 处理器将来自请求队列的优先消息和相关联的认证信息传送到安全硬件引擎。 响应于从处理器接收优先化的消息和相关联的认证信息，安全硬件引擎认证消息。 安全硬件引擎将经认证的消息传送到处理器以存储在结果队列中。

公开(公告)号：US20180365080A1

公开(公告)日：2018-12-20

申请号：US15625051

申请日：2017-06-16

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  STEPHEN G. LUSKO

IPC: G06F9/52 ,  G06F17/30

CPC classification number: G06F9/52 ,  G06F16/27

Abstract: A synchronization method in a multiprocessor system is provided. The method includes providing a plurality of synchronization mechanisms for synchronizing data to be accessed by a plurality of concurrently executable tasks, analyzing design information and runtime information for application software that includes the concurrently executable tasks, identifying, based on the analysis, software architecture patterns for the concurrently executable tasks that access a shared variable, and associating, based on the analysis, each of the software architecture patterns to one or more of the synchronization mechanisms. The method further includes generating synchronization table entries for a synchronization table that identify the shared variable, the software architecture pattern for the concurrently executable tasks that access the shared variable, and the one or more synchronization mechanisms associated with the software architecture pattern and also includes accessing the shared variable using the one or more synchronization mechanisms identified in the synchronization table.

公开(公告)号：US20170147495A1

公开(公告)日：2017-05-25

申请号：US14951656

申请日：2015-11-25

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHUQING ZENG ,  SHIGE WANG ,  STEPHEN G. LUSKO

IPC: G06F12/08

CPC classification number: G06F12/0868 ,  G06F9/00 ,  G06F9/30 ,  G06F2212/1008 ,  G06F2212/281 ,  G06F2212/452

Abstract: A method of ordering memory access by an instruction cache of a central processing unit on a global memory device. A signal list of a link map file is extracted in the global memory device. Memory access traces relating to executed tasks are accessed from the signal list. Memory locations accessed in the global memory device from the access traces are identified. A correlation value for each pair of memory locations accessed in the global memory device is determined. Correlation values of the pairs of memory locations are determined, wherein the correlation values are computed based on a proximity of executable instructions utilizing the respective pair of memory locations. Accessed memory locations within the global memory device are reordered as a function of the determined correlation values. An executable file accessing the global memory device is modified.

公开(公告)号：US20160314031A1

公开(公告)日：2016-10-27

申请号：US14696834

申请日：2015-04-27

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  CHANG LIU ,  JOSEPH G. D'AMBROSIO

IPC: G06F11/07

CPC classification number: G06F11/076 ,  G06F11/0721

Abstract: A method of adaptively reconfiguring controller functions during a frame overrun. A frame overrun condition is detected. A respective task from a plurality of tasks is identified as a largest contributor to the frame overrun. A mode associated with the identified task is identified to correct the frame overrun. Functions are reallocated within the identified task to one or more other tasks until the frame overrun condition is corrected. Respective functions reallocated are identified as a function of the identified mode.

Abstract translation: 一种在帧超限期间自适应地重新配置控制器功能的方法。 检测到帧溢出条件。 来自多个任务的相应任务被识别为帧超限的最大贡献者。 识别与识别的任务相关联的模式以校正帧超限。 将功能在所识别的任务内重新分配到一个或多个其他任务，直到帧超限状态得到纠正。 重新分配的各种功能被识别为所识别模式的函数。

公开(公告)号：US20150347279A1

公开(公告)日：2015-12-03

申请号：US14294337

申请日：2014-06-03

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： RAMESH SETHU ,  SHIGE WANG

IPC: G06F11/36

CPC classification number: G06F11/3684 ,  G06F11/3636 ,  G06F11/368

Abstract: A method of establishing traceability for embedded software systems. A design code database is provided for an embedded software system. A test suite database including a plurality of test cases is structured for testing design code of the embedded software system. The structuring of the test cases provides a correspondence from a respective test case to a respective portion of the design code. A processor receives a design code modification to the embedded software. An associated test case is identified for testing the modified design code being based on traceability data. The associated test case is revised to accommodate the modified design code. The modified test cases are integrated into the test suite. A traceability database establishes a one-to-one correspondence between the modified design coder and the modified test case is updated.

Abstract translation: 一种为嵌入式软件系统建立可追溯性的方法。 为嵌入式软件系统提供设计代码数据库。 包括多个测试用例的测试套件数据库被构造用于测试嵌入式软件系统的设计代码。 测试用例的结构化提供了从相应测试用例到设计代码的相应部分的对应关系。 处理器接收嵌入式软件的设计代码修改。 识别相关的测试用例，用于测试基于可追溯性数据的修改后的设计代码。 修改相关测试用例以适应修改后的设计代码。 修改后的测试用例集成到测试套件中。 可追溯性数据库在修改后的设计编码器和修改的测试用例之间建立一对一的对应关系。

公开(公告)号：US20180292988A1

公开(公告)日：2018-10-11

申请号：US15482195

申请日：2017-04-07

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  J. DAVID ROSA

IPC: G06F3/06 ,  G06F12/12 ,  G06F13/16

Abstract: A memory access method in a multicore processor integrated circuit (IC) is provided. The method comprises partitioning local memory on the IC into a plurality of memory regions wherein each memory region comprises one or more memory segments and assigning each memory region to one or more processing entities or applications wherein each processing entity comprises a processor core or a processing device that is under the control of a processor core and wherein the application is capable of being performed by one of the processing entities. The method further comprises monitoring, with each processing entity, the usage of each memory segment in each region assigned to the processing entity and assigned to the applications performed by the processing entity and swapping the data in a memory segment from a memory region experiencing a miss for desired data when the miss causes a data access with external memory.

公开(公告)号：US20170277604A1

公开(公告)日：2017-09-28

申请号：US15078255

申请日：2016-03-23

Applicant: GM GLOBAL TECHNOLOGY OPERATIONS LLC

Inventor： SHIGE WANG ,  XIAOFENG F. SONG ,  XIAN ZHANG

IPC: G06F11/18

CPC classification number: G06F11/182 ,  G05B19/0421 ,  G06F2201/805 ,  G06F2201/82

Abstract: A method of arbitrating conflicting outputs in a redundant control system. Execution data of a task executed by each controller in the redundant control system is recorded. The execution data includes an initial timestamp of each execution stream, identification of critical functions in each execution stream, and parameter values used by the critical functions. A path executed by each controller is identified based only on the critical functions executed for each execution stream. The recorded execution data of each executed path is applied to an arbitration module. An output result from one of the respective controllers selecting, by an arbitration module, based on the recorded execution data of each executed path. The output result of the selected controller is communicated to a next module for further processing.