公开(公告)号：US5574896A

公开(公告)日：1996-11-12

申请号：US608101

申请日：1996-02-28

申请人： Gabriel M. Li ,  Hee Wong

发明人： Gabriel M. Li ,  Hee Wong

IPC分类号： H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0608

摘要： A framing circuit, which frames bytes of data received from a serial data bit stream, prevents a short byte clock pulse from being formed when the byte clock signal, which identifies the beginning of each frame, is reset. The framing circuit utilizes a comparison stage to output a match signal each time an n-bit data bit pattern matches a programmable predetermined framing pattern, and to delay each n-bit pattern a delay time. The framing circuit also utilizes a counter to produce the byte clock signal, and a delay circuit to freeze the output of the counter for a predetermined delay time each time the match signal is output. The delay circuit also resets the byte clock signal so that the reset byte clock signal coincides with the output of the delayed data bit pattern. By freezing the output of the counter for a predetermined time, the width of the resulting pulse is lengthened.

摘要翻译： 当识别出每帧的开始的字节时钟信号被复位时，从串行数据比特流接收的帧数据的成帧电路防止形成短字节时钟脉冲。 成帧电路利用比较级在每次n位数据位模式与可编程预定成帧模式匹配时输出匹配信号，并且延迟每个n位模式延迟时间。 成帧电路还利用计数器产生字节时钟信号，以及每当输出匹配信号时将计数器的输出冻结预定延迟时间的延迟电路。 延迟电路还复位字节时钟信号，使得复位字节时钟信号与延迟的数据位模式的输出一致。 通过将计数器的输出冻结预定时间，所得到的脉冲的宽度被延长。

公开(公告)号：US5477177A

公开(公告)日：1995-12-19

申请号：US371013

申请日：1995-01-11

申请人： Hee Wong ,  Gabriel M. Li

发明人： Hee Wong ,  Gabriel M. Li

IPC分类号： H03L7/085 ,  H03L7/099 ,  H04L7/00 ,  H04L7/033 ,  H03L7/08 ,  H03D3/20

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H04L7/033 ,  H04L7/0083

摘要： A phase-locked loop having a phase error processor (PEP) circuit in which a phase error is provided to the PEP circuit in the form of a first pulse stream comprising pulses of a width dictated by the phase error between the incoming data and a local clock and a second pulse stream comprising pulses of a reference width. The circuit includes two integrators having outputs coupled to first and second inputs of a comparator, respectively. Switches couple the first pulse stream to the input of one integrator and the second pulse stream to the input of the other integrator during a first time window and reverse the connections during a second time window. The switches are controlled by a SWAP signal which alternates state at regular intervals. The output of the comparator is exclusive-ORed with the SWAP signal in order to invert the comparator output signal every other window so as to average any input offset error of the comparator or offset due to mismatch of the integrators evenly between the two pulse streams. The output of the exclusive-OR gate is coupled to the input of a D flip flop which is latched once per window. The output of the D flip flop is an UP/DOWN signal which controls an oscillator, which generates the local clock signal, to advance or retard the phase of the local clock in response to the condition of the UP/DOWN signal.

摘要翻译： 一种具有相位误差处理器（PEP）电路的锁相环，其中以第一脉冲流的形式向PEP电路提供相位误差，该第一脉冲流包括由输入数据与本地信号之间的相位误差指定的宽度的脉冲 时钟和包括参考宽度的脉冲的第二脉冲流。 电路包括两个积分器，分别具有耦合到比较器的第一和第二输入的输出。 在第一时间窗口期间，开关将第一脉冲流耦合到一个积分器的输入，将第二脉冲流耦合到另一个积分器的输入端，并在第二时间窗口期间反向连接。 开关由SWAP信号控制，SWAP信号以规则的间隔交替状态。 比较器的输出与SWAP信号异或，以便每隔一个窗口反相比较器输出信号，以便平均比较器的任何输入偏移误差或由于两个脉冲流之间的积分器不匹配引起的偏移。 异或门的输出耦合到D触发器的输入，每个窗口被锁存一次。 D触发器的输出是UP /＆amp; upbar＆D信号，其控制产生本地时钟信号的振荡器，以响应于UP /＆amp; upbar＆D信号的条件来推进或延迟本地时钟的相位。

公开(公告)号：US07368960B2

公开(公告)日：2008-05-06

申请号：US11153759

申请日：2005-06-15

申请人： Gabriel M. Li ,  Greg J. Richmond

发明人： Gabriel M. Li ,  Greg J. Richmond

IPC分类号： H03L7/00

CPC分类号： G06F1/28 ,  G01R19/16552

摘要： Circuits and methods are provided herein for monitoring the integrity of a power supply, the circuits and methods providing additional resources/information for diagnosing a cause behind a reset signal, and in some cases, a reason behind a power failure. A first method described herein provides exemplary steps for monitoring a level of a power supply voltage supplied to one or more system components. A second method describes exemplary steps for monitoring an electrical connection between the power supply (or ground supply) and one or more supply pins. Each of the methods involves monitoring a state of one or more bits stored, e.g., within a status register. The methods may be used separately, or in conjunction with one another, for detecting the occurrence of a power abnormality.

摘要翻译： 本文提供了用于监测电源的完整性的电路和方法，所述电路和方法提供用于诊断复位信号背后的原因的附加资源/信息，并且在一些情况下是电源故障背后的原因。 本文描述的第一种方法提供了用于监测提供给一个或多个系统组件的电源电压的电平的示例性步骤。 第二种方法描述了用于监测电源（或接地电源）和一个或多个电源引脚之间的电连接的示例性步骤。 每种方法涉及监视存储在例如状态寄存器内的一个或多个位的状态。 这些方法可以单独使用，也可以彼此结合使用，用于检测功率异常的发生。

公开(公告)号：US5058132A

公开(公告)日：1991-10-15

申请号：US427794

申请日：1989-10-26

申请人： Gabriel M. Li

发明人： Gabriel M. Li

IPC分类号： G06F1/04 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0685

摘要： A clock distribution device (CDD) (100) is used in a concentrator (200,300) to distribute multiple bits of serial data (208) in parallel across back plane boards (Board A, B, N. NN) as a byte-wide data signal (214). Each back plane board (Board A, B, N, NN) has a CDD (100). One back plane board (Board A) has a master oscillator (120) which generates a local low frequency reference clock signal (212). The reference clock signal (212) is distributed to all of the back plane boards (Board A, B, N, NN) where each board's CDD (100) uses the reference clock signal (212) to generate a high frequency clock signal (TXCLK) and a plurality of local phase separated clock signals (LBC1-LBC5). Each board has a receiver (156a) and a transmitter (156b) and the low frequency clock signals (LBC1-LBC5) are employed to synchronize and deskew the parallel data signal (214) transmitted across the back plane from board to board by using the local phase separated clock signals (LBC1-LBC5) generated on each board to strobe out the serial data (208) from the receiver (156a) in parallel as the parallel data signal (214), to latch in the parallel data signal (214) into a latch (LATCH) internal to the transmitter (156b), to enable a storage register (TXSR) on the transmitter (156b) which stores the parallel data signal (214) for conversion back to serial data, and to strobe in the parallel data signal (214) into a latch (170) when the CDD (100) is used in a large concentrator (300).

公开(公告)号：US4626711A

公开(公告)日：1986-12-02

申请号：US609368

申请日：1984-05-11

申请人： Gabriel M. Li

发明人： Gabriel M. Li

IPC分类号： H03K17/0422 ,  H03K19/013 ,  H03K19/21 ,  H03K19/092

CPC分类号： H03K19/013 ,  H03K17/0422 ,  H03K19/212

摘要： An exclusive-or circuit which is extremely fast, uses lower power and fewer components, and is easier to manufacture than prior art circuits is achieved in a circuit which uses only a single reference voltage potential (shown as positive) in the portion of the circuit which generates exclusive-nor logic, and uses a feedback transistor to prevent saturation of a switching transistor. In the off state of the switching transistor, the single reference potential causes the base to be several saturation potentials above ground. In the on state, the feedback transistor reduces the base current. Thus the voltage swing between on and off states is less than in prior art circuits. In addition, the logic from many input signals can be combined to create a single exclusive-nor signal before buffering to an exclusive-or signal at the output terminal.

摘要翻译： 在电路部分中仅使用单个参考电压电位（显示为正）的电路中，实现了非常快的专用或电路，使用较低功率和更少的部件，并且比现有技术电路更容易制造， 其产生异或逻辑，并且使用反馈晶体管来防止开关晶体管的饱和。 在开关晶体管的截止状态下，单个参考电位使基极为地上几个饱和电位。 在导通状态下，反馈晶体管降低基极电流。 因此，开和关状态之间的电压摆动小于现有技术电路中的电压摆幅。 此外，来自许多输入信号的逻辑可以被组合以在缓冲到输出端子处的异或信号之前产生单独的异或信号。

公开(公告)号：US07454645B2

公开(公告)日：2008-11-18

申请号：US11097527

申请日：2005-03-31

申请人： Gabriel M. Li ,  Greg J. Richmond ,  Sangeeta Raman

发明人： Gabriel M. Li ,  Greg J. Richmond ,  Sangeeta Raman

IPC分类号： G06F1/00 ,  G06F1/14

CPC分类号： H03K5/26 ,  G01R23/005 ,  G06F1/12 ,  H03K5/19

摘要： A circuit and method are provided herein for monitoring the status of a clock signal. In general, the method may include supplying a pair of clock signals to a clock monitor circuit, which is configured for monitoring a status of one clock signal relative to the other. The status indicates whether the frequency of the one clock signal is faster, slower or substantially equal to the frequency of the other clock signal. Once determined, the status may be stored as a bit pattern within a status register, which is operatively coupled to the clock monitor circuit. This enables the status to be read by detecting a logic state of one or more bits within the status register.

摘要翻译： 本文提供了一种用于监视时钟信号的状态的电路和方法。 通常，该方法可以包括将一对时钟信号提供给时钟监控电路，时钟监视电路被配置为监视相对于另一个时钟信号的一个时钟信号的状态。 该状态指示一个时钟信号的频率是否比其他时钟信号的频率更快，更慢或基本上等于其他时钟信号的频率。 一旦确定，状态可以作为位模式存储在状态寄存器内，状态寄存器可操作地耦合到时钟监视器电路。 这样可以通过检测状态寄存器中的一个或多个位的逻辑状态来读取状态。

公开(公告)号：US07295051B2

公开(公告)日：2007-11-13

申请号：US11153773

申请日：2005-06-15

申请人： Gabriel M. Li ,  Greg J. Richmond

发明人： Gabriel M. Li ,  Greg J. Richmond

IPC分类号： H03L7/00 ,  H03K3/02

CPC分类号： G06F1/28

摘要： A system and method are provided herein for monitoring the integrity of a power supply by monitoring a level of the power supply voltage supplied to one or more system components. The method, as described herein, includes setting a bit in a status register after the power supply level reaches a threshold level, and monitoring a state of the bit to determine if the power supply level has dropped below the threshold level. For example, the method may determine that the power supply level has dropped below the threshold level if the state of the bit changes from a set bit to a cleared bit. In addition, the system and method described herein may be used for detecting the occurrence of a power abnormality by providing additional resources/information about a power related event.

公开(公告)号：US07069458B1

公开(公告)日：2006-06-27

申请号：US10222129

申请日：2002-08-16

申请人： Mohamed Sardi ,  Gabriel M. Li

发明人： Mohamed Sardi ,  Gabriel M. Li

IPC分类号： G06F13/42

CPC分类号： H04L7/0338 ,  H03L7/0996

摘要： A parallel data interface and method is provided herein, which adjusts a timing relationship of a clock signal to not only minimize clock skew, but to also compensate for noise components that may affect one or more paths of a parallel data bus. In some embodiments, the parallel data interface includes a first phase generator coupled to generate a first plurality of time delay pulses, and a first phase selector adapted to select one of the first plurality of time delay pulses to adjust the timing of a clock signal to sample each and every one of the plurality of data signals between minimum setup and hold time thresholds. In some embodiments, the parallel data interface includes a second phase generator coupled to generate a second plurality of time delay pulses, and a second phase selector adapted to select one of the second plurality of time delay pulses to adjust the timing of the clock signal to output the plurality of data signals from the data interface at least an amount of time (i.e., an access time) after the adjusted clock transition is output from the data interface.

摘要翻译： 本文提供并行数据接口和方法，其调整时钟信号的定时关系，以便不仅最小化时钟偏差，而且还补偿可能影响并行数据总线的一个或多个路径的噪声分量。 在一些实施例中，并行数据接口包括耦合以产生第一多个时间延迟脉冲的第一相位发生器，以及适于选择第一多个时间延迟脉冲之一以调整时钟信号定时的第一相位选择器 在最小建立和保持时间阈值之间对多个数据信号中的每一个进行采样。 在一些实施例中，并行数据接口包括耦合以产生第二多个时间延迟脉冲的第二相位发生器，以及适于选择第二多个时间延迟脉冲之一以调整时钟信号定时的第二相位选择器 在从数据接口输出调整后的时钟转移之后，从数据接口输出多个数据信号至少一段时间（即访问时间）。

公开(公告)号：US5179664A

公开(公告)日：1993-01-12

申请号：US338587

申请日：1989-04-14

申请人： Gabriel M. Li ,  James R. Hamstra

发明人： Gabriel M. Li ,  James R. Hamstra

IPC分类号： H04L13/08 ,  H04J3/06 ,  H04L7/00

CPC分类号： H04J3/0632

摘要： A symbol-wide elasticity buffer for a receive/transmit station within an asynchronous data transmission network provides both for reframing after each packet and for the handling of a continuous line state symbol for a period longer than the allowed packet size. According to one aspect of the invention, the elasticity buffer is divided into a START section and a CONTINUATION section. The buffer's write pointer will not enter the CONTINUATION section until the read pointer is directed to the first of the multiple, sequential registers comprising the START section. The read pointer must sequentially read the START section registers before entering the CONTINUATION section. Once the write pointer or read pointer leaves the START section, it can only reenter the START section upon receipt of a start delimiter signal. When the write pointer or the read pointer reaches the last register in the CONTINUATION section, it is automatically routed back to the first CONTINUATION section register. According to a second aspect of the invention, a repeat flag is associated with the last register in the CONTINUATION section. The repeat flag is set upon receipt of any repeatable control signal. With the Repeat Flag set, the read pointer will reach the final CONTINUATION section register and continue to read the same symbol without causing an overflow or underflow. When a new symbol is received, a CONTINUE signal is generated and the write pointer begins writing to the CONTINUATION section. After a predetermined delay, the read pointer begins reading the first register in the CONTINUATION section and the R-Flag is cleared.

公开(公告)号：US4984251A

公开(公告)日：1991-01-08

申请号：US394445

申请日：1989-08-16

申请人： Ronald S. Perloff ,  James R. Hamstra ,  Gabriel M. Li ,  Louise Y. Y. Yeung

发明人： Ronald S. Perloff ,  James R. Hamstra ,  Gabriel M. Li ,  Louise Y. Y. Yeung

IPC分类号： H04J3/06

CPC分类号： H04J3/0632 ,  H04J3/0608

摘要： A method and apparatus for synchronizing the cascaded, multi-channel transmission of a plurality of data characters is provided. Each sequence of data characters preceded by a start delimiter. Each transmission channel provides transmitted data frames to an associated elasticity buffer. As each channel detects a start delimiter, it asserts a begin-request signal that acknowledges detection of the start delimiter. When all channels have detected a start delimiter, a read-start signal is asserted to simultaneously advance the read pointer of each elasticity buffer. In this manner, each elasticity buffer initiates a sunchronized read for local use or retransmission of the multi-channel data.

摘要翻译： 提供了一种用于同步多个数据字符的级联多通道传输的方法和装置。 每个序列的数据字符都以起始分隔符前面。 每个传输通道将传输的数据帧提供给相关联的弹性缓冲器。 当每个通道检测到一个起始分隔符时，它断言一个确认起始分隔符检测的开始请求信号。 当所有通道都检测到起始分隔符时，一个读取 - 开始信号被断言，以同时推进每个弹性缓冲器的读取指针。 以这种方式，每个弹性缓冲器启动用于本地使用或重发多通道数据的同步读取。