公开(公告)号：US20200176360A1

公开(公告)日：2020-06-04

申请号：US16203777

申请日：2018-11-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Ramanujam Ramabhadran ,  Kum-Kang Huh ,  Brian Lynn Rowden ,  Glenn Scott Claydon ,  Ahmed Elasser

IPC: H01L23/498 ,  H01L23/64 ,  H01L23/538 ,  H01L21/56 ,  H01L23/00 ,  H01L29/20

Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.

公开(公告)号：US10770382B2

公开(公告)日：2020-09-08

申请号：US16203777

申请日：2018-11-29

Applicant: General Electric Company

Inventor： Christopher James Kapusta ,  Ramanujam Ramabhadran ,  Kum-Kang Huh ,  Brian Lynn Rowden ,  Glenn Scott Claydon ,  Ahmed Elasser

IPC: H01L23/498 ,  H01L23/64 ,  H01L23/538 ,  H01L23/00 ,  H01L29/20 ,  H01L21/56

Abstract: A modular electronics package is disclosed that includes a first and second electronics packages, with each of the first and second electronics packages including a metallized insulating substrate and a solid-state switching device positioned on the metallized insulating substrate, the solid-state switching device comprising a plurality of contact pads electrically coupled to the first conductor layer of the metallized insulating substrate. A conductive joining material is positioned between the first electronics package and the second electronics package to electrically connect them together. The first electronics package and the second electronics package are stacked with one another to form a half-bridge unit cell, with the half-bridge unit cell having a current path through the solid-state switching device in the first electronics package and a close coupled return current path through the solid-state switching device in the second electronics package in opposite flow directions.

公开(公告)号：US20140167248A1

公开(公告)日：2014-06-19

申请号：US13720351

申请日：2012-12-19

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H01L23/46 ,  H01L25/00

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/46 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/00

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract translation: 集成功率模块包括具有至少一个切出区域的基本上平面的绝缘金属基板; 设置在所述切出区域内的至少一个基本上平面的陶瓷基板，其中所述陶瓷基板通过所述绝缘金属基板在至少两侧框架，所述陶瓷基板包括在第一侧上的第一金属层和在第一侧上的第二金属层 第二面 耦合到陶瓷衬底的第一侧的至少一个功率半导体器件; 耦合到所述绝缘金属基板的第一表面的至少一个控制装置; 功率覆盖层，电连接所述至少一个半导体功率器件和所述至少一个控制器件; 以及可操作地连接到所述至少一个陶瓷基板的第二金属层的冷却流体储存器，其中在所述冷却流体储存器中设置多个冷却流体通道。

公开(公告)号：US10347608B2

公开(公告)日：2019-07-09

申请号：US15605686

申请日：2017-05-25

Applicant: General Electric Company

Inventor： Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic

IPC: H01L25/07 ,  H01L29/16 ,  H02M7/00 ,  H01L23/64

Abstract: A power module includes a first bus bar having a first plurality of tabs, wherein each of the first plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a first side; a second bus bar having a second plurality of tabs, wherein each of the second plurality of tabs is electrically coupled to a respective conductive trace of a plurality of conductive traces disposed on a second side; and a third bus bar having a third plurality of tabs, wherein at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the first side and at least one tab of the third plurality of tabs is electrically coupled to a respective conductive trace of the plurality of conductive traces disposed on the second side.

公开(公告)号：US20140133104A1

公开(公告)日：2014-05-15

申请号：US13675084

申请日：2012-11-13

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H05K7/20

CPC classification number: H01L24/19 ,  H01L23/3735 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

Abstract: A surface mount package includes at least one semiconductor device and a POL packaging and interconnect system formed about the at least one semiconductor device that is configured enable mounting of the surface mount package to an external circuit. The POL system includes a dielectric layer overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias formed through the dielectric layer so as to be electrically coupled to connection pads on the semiconductor device(s). A metallization layer is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate is positioned on a second surface of the semiconductor device(s), with the double-sided ceramic substrate being configured to electrically isolate a drain of the semiconductor device(s) from an external circuit when the surface mount package is joined thereto and to conduct heat away from the semiconductor device(s).

Abstract translation: 表面安装封装包括至少一个半导体器件和围绕所述至少一个半导体器件形成的POL封装和互连系统，该半导体器件被配置为能够将表面贴装封装安装到外部电路。 POL系统包括覆盖半导体器件的第一表面的电介质层和延伸穿过通过介电层形成的通孔的金属互连结构，以便电耦合到半导体器件上的连接焊盘。 在包括平面结构的金属互连结构上形成金属化层，并且双面陶瓷衬底位于半导体器件的第二表面上，双面陶瓷衬底被配置为电隔离 当表面安装封装与其连接时，半导体器件从外部电路漏极，并将热量从半导体器件导出。

公开(公告)号：US09972569B2

公开(公告)日：2018-05-15

申请号：US15482228

申请日：2017-04-07

Applicant: General Electric Company

Inventor： Brian Lynn Rowden ,  Ljubisa Dragoljub Stevanovic

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/49 ,  H01L23/492 ,  H01L23/495 ,  H01L23/50 ,  H01L25/00 ,  H01L25/18 ,  H01L25/07

CPC classification number: H01L23/50 ,  H01L23/142 ,  H01L23/49 ,  H01L23/492 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/49575 ,  H01L24/48 ,  H01L24/49 ,  H01L25/072 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/05552 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45014 ,  H01L2224/48245 ,  H01L2224/48472 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/85205 ,  H01L2924/00014 ,  H01L2924/19107 ,  H01L2224/45099

Abstract: A method and system for a power module is provided. The power module includes a first substrate including a first conductive substrate having a first plurality of power semiconductor switches arranged thereon, and at least one second conductive substrate electrically coupled to the first conductive substrate. A first terminal is electrically coupled to the first conductive substrate. The power module also includes a second substrate including a third conductive substrate having a second plurality of power semiconductor switches arranged thereon, and at least one fourth conductive substrate electrically coupled to the third conductive substrate. The third conductive substrate is electrically coupled to the second conductive substrate. A second terminal is electrically coupled to the fourth conductive substrate.

公开(公告)号：US09337163B2

公开(公告)日：2016-05-10

申请号：US13675084

申请日：2012-11-13

Applicant: General Electric Company

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H05K7/20 ,  H01L23/00 ,  H01L23/373 ,  H01L23/498 ,  H01L23/538

CPC classification number: H01L24/19 ,  H01L23/3735 ,  H01L23/49805 ,  H01L23/49844 ,  H01L23/49894 ,  H01L23/5385 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/92 ,  H01L2224/0401 ,  H01L2224/04026 ,  H01L2224/06181 ,  H01L2224/12105 ,  H01L2224/24137 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/82005 ,  H01L2224/82031 ,  H01L2224/82039 ,  H01L2224/82047 ,  H01L2224/83424 ,  H01L2224/83447 ,  H01L2224/92144 ,  H01L2225/1035 ,  H01L2924/10272 ,  H01L2924/1203 ,  H01L2924/12042 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/351 ,  H01L2924/014 ,  H01L2924/00

Abstract: A surface mount package includes at least one semiconductor device and a POL packaging and interconnect system formed about the at least one semiconductor device that is configured enable mounting of the surface mount package to an external circuit. The POL system includes a dielectric layer overlying a first surface of the semiconductor device(s) and a metal interconnect structure extending through vias formed through the dielectric layer so as to be electrically coupled to connection pads on the semiconductor device(s). A metallization layer is formed over the metal interconnect structure that comprises a flat planar structure, and a double-sided ceramic substrate is positioned on a second surface of the semiconductor device(s), with the double-sided ceramic substrate being configured to electrically isolate a drain of the semiconductor device(s) from an external circuit when the surface mount package is joined thereto and to conduct heat away from the semiconductor device(s).

Abstract translation: 表面安装封装包括至少一个半导体器件和围绕所述至少一个半导体器件形成的POL封装和互连系统，该半导体器件被配置为能够将表面贴装封装安装到外部电路。 POL系统包括覆盖半导体器件的第一表面的电介质层和延伸穿过通过介电层形成的通孔的金属互连结构，以便电耦合到半导体器件上的连接焊盘。 在包括平面结构的金属互连结构上形成金属化层，并且双面陶瓷衬底位于半导体器件的第二表面上，双面陶瓷衬底被配置为电隔离 当表面安装封装与其连接时，半导体器件从外部电路漏极，并将热量从半导体器件导出。

公开(公告)号：US09142484B2

公开(公告)日：2015-09-22

申请号：US14509666

申请日：2014-10-08

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H01L23/427 ,  H01L23/373 ,  H01L23/473 ,  H01L23/46 ,  H01L25/00 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/46 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/00

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract translation: 集成功率模块包括具有至少一个切出区域的基本上平面的绝缘金属基板; 设置在所述切出区域内的至少一个基本上平面的陶瓷基板，其中所述陶瓷基板通过所述绝缘金属基板在至少两侧框架，所述陶瓷基板包括在第一侧上的第一金属层和在第一侧上的第二金属层 第二面 耦合到陶瓷衬底的第一侧的至少一个功率半导体器件; 耦合到所述绝缘金属基板的第一表面的至少一个控制装置; 功率覆盖层，电连接所述至少一个半导体功率器件和所述至少一个控制器件; 以及可操作地连接到所述至少一个陶瓷基板的第二金属层的冷却流体储存器，其中在所述冷却流体储存器中设置多个冷却流体通道。

公开(公告)号：US20150024553A1

公开(公告)日：2015-01-22

申请号：US14509666

申请日：2014-10-08

Applicant: GENERAL ELECTRIC COMPANY

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H01L23/473 ,  H01L23/00

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/46 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/00

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract translation: 集成功率模块包括具有至少一个切出区域的基本上平面的绝缘金属基板; 设置在所述切出区域内的至少一个基本上平面的陶瓷基板，其中所述陶瓷基板通过所述绝缘金属基板在至少两侧框架，所述陶瓷基板包括在第一侧上的第一金属层和在第一侧上的第二金属层 第二面 耦合到陶瓷衬底的第一侧的至少一个功率半导体器件; 耦合到所述绝缘金属基板的第一表面的至少一个控制装置; 功率覆盖层，电连接所述至少一个半导体功率器件和所述至少一个控制器件; 以及可操作地连接到所述至少一个陶瓷基板的第二金属层的冷却流体储存器，其中在所述冷却流体储存器中设置多个冷却流体通道。

公开(公告)号：US08872328B2

公开(公告)日：2014-10-28

申请号：US13720351

申请日：2012-12-19

Applicant: General Electric Company

Inventor： Eladio Clemente Delgado ,  John Stanley Glaser ,  Brian Lynn Rowden

IPC: H01L23/46 ,  H05K7/20 ,  H01L25/00

CPC classification number: H01L23/473 ,  H01L23/13 ,  H01L23/3735 ,  H01L23/46 ,  H01L24/19 ,  H01L24/24 ,  H01L24/83 ,  H01L25/50 ,  H01L2224/04105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/32225 ,  H01L2224/73267 ,  H01L2224/83815 ,  H01L2224/92144 ,  H01L2224/9222 ,  H01L2924/01029 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/15787 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/20105 ,  H01L2924/20106 ,  H01L2924/00

Abstract: An integrated power module includes a substantially planar insulated metal substrate having at least one cut-out region; at least one substantially planar ceramic substrate disposed within the cut-out region, wherein the ceramic substrate is framed on at least two sides by the insulated metal substrate, the ceramic substrate including a first metal layer on a first side and a second metal layer on a second side; at least one power semiconductor device coupled to the first side of the ceramic substrate; at least one control device coupled to a first surface of the insulated metal substrate; a power overlay electrically connecting the at least one semiconductor power device and the at least one control device; and a cooling fluid reservoir operatively connected to the second metal layer of the at least one ceramic substrate, wherein a plurality of cooling fluid passages are provided in the cooling fluid reservoir.

Abstract translation: 集成功率模块包括具有至少一个切出区域的基本上平面的绝缘金属基板; 设置在所述切出区域内的至少一个基本上平面的陶瓷基板，其中所述陶瓷基板通过所述绝缘金属基板在至少两侧框架，所述陶瓷基板包括在第一侧上的第一金属层和在第一侧上的第二金属层 第二面 耦合到陶瓷衬底的第一侧的至少一个功率半导体器件; 耦合到所述绝缘金属基板的第一表面的至少一个控制装置; 功率覆盖层，电连接所述至少一个半导体功率器件和所述至少一个控制器件; 以及可操作地连接到所述至少一个陶瓷基板的第二金属层的冷却流体储存器，其中在所述冷却流体储存器中设置多个冷却流体通道。