公开(公告)号：US06459325B1

公开(公告)日：2002-10-01

申请号：US09832149

申请日：2001-04-11

申请人： Geoffrey B. Hall ,  Fujio Takeda ,  Michael Priel

发明人： Geoffrey B. Hall ,  Fujio Takeda ,  Michael Priel

IPC分类号： H03K1716

CPC分类号： H03K17/163 ,  H03K4/00 ,  H03K17/6872

摘要： An output buffer (100) has a pre-driver circuit (120) for controlling a voltage transition of an output signal from an output driver transistor (150). The pre-driver circuit (120) provides an input that slightly leads the gate voltage of the output driver transistor (150). The pre-driver circuit (120) includes a configurable resistance circuit (480) that provides one resistance value at the start of a signal transition and provides another resistance value near the end of the signal transition. A threshold detector (470) senses a voltage level of the input signal and switches from one resistance value to the other resistance value when the input signal crosses a predetermined voltage.

摘要翻译： 输出缓冲器（100）具有用于控制来自输出驱动晶体管（150）的输出信号的电压转换的预驱动电路（120）。 预驱动器电路（120）提供稍微导致输出驱动晶体管（150）的栅极电压的输入。 预驱动器电路（120）包括在信号转换开始时提供一个电阻值的可配置电阻电路（480），并且在信号转换结束附近提供另一个电阻值。 当输入信号越过预定电压时，阈值检测器（470）感测输入信号的电压电平并从一个电阻值切换到另一个电阻值。

公开(公告)号：US09906355B2

公开(公告)日：2018-02-27

申请号：US14758973

申请日：2013-01-09

申请人： Michael Priel ,  Leonid Fleshel ,  Roman Mostinski ,  Vladimir Nusimovich

发明人： Michael Priel ,  Leonid Fleshel ,  Roman Mostinski ,  Vladimir Nusimovich

IPC分类号： H04L7/00 ,  G11C19/00 ,  G01R31/317 ,  G01R31/28

CPC分类号： H04L7/00 ,  G01R31/2837 ,  G01R31/2884 ,  G01R31/31712 ,  G11C19/00

摘要： There is provided a method, apparatus and integrated circuit for measuring a signal, the apparatus comprising a plurality of sample stages arranged in series, each sample stage comprising a delay element, and a sample element, wherein an input of the sample element is coupled to an output of the delay element, and a strobe line for controlling a sample time of the sample elements, the strobe line comprising a plurality of strobe delay elements arranged in series, wherein an output of each strobe delay element is coupled to one or more sample elements.

公开(公告)号：US09503088B2

公开(公告)日：2016-11-22

申请号：US14655150

申请日：2013-01-10

申请人： Sergey Sofer ,  Michael Priel ,  Noam Sivan

发明人： Sergey Sofer ,  Michael Priel ,  Noam Sivan

IPC分类号： H03K19/003 ,  H03K19/0944

CPC分类号： H03K19/00384 ,  H03K19/0944

摘要： The invention provides a method for recovering NBTI/PBTI related parameter degradation in MOSFET devices. The method includes operating the at least one MOSFET device in a standby mode, exiting the at least one MOSFET device from the standby mode, holding the at least one MOSFET device in an active state for a predetermined time span after exiting the standby mode, and operating the at least one MOSFET device in an operational mode after the predetermined time span has elapsed.

摘要翻译： 本发明提供一种用于恢复MOSFET器件中的NBTI / PBTI相关参数劣化的方法。 该方法包括在备用模式下操作至少一个MOSFET器件，将至少一个MOSFET器件从备用模式退出，在退出待机模式之后将至少一个MOSFET器件保持在预定时间间隔内的活动状态;以及 在经过预定时间间隔之后，在操作模式下操作至少一个MOSFET器件。

公开(公告)号：US09413351B2

公开(公告)日：2016-08-09

申请号：US14122556

申请日：2011-06-15

申请人： Sergey Sofer ,  Valery Neiman ,  Michael Priel

发明人： Sergey Sofer ,  Valery Neiman ,  Michael Priel

IPC分类号： G06F1/26 ,  G06F1/32 ,  H03K17/687 ,  H03K17/00 ,  H03K19/00

CPC分类号： H03K17/6871 ,  G06F1/26

摘要： An integrated circuit device comprises at least one power gating arrangement, including at least one gated power domain, and at least one power gating component operably coupled between at least one node of the at least one gated power domain and at least a first power supply node. The at least one power gating component is arranged to selectively couple the at least one node of the at least one gated power domain to the at least first power supply node.

摘要翻译： 集成电路装置包括至少一个电源门控装置，其包括至少一个门控功率域，以及至少一个功率选通组件，其可操作地耦合在所述至少一门机功率域的至少一个节点与至少第一电源节点 。 所述至少一个电源门控部件被布置成选择性地将所述至少一个门控功率域的至少一个节点耦合到所述至少第一电源节点。

公开(公告)号：US09368162B2

公开(公告)日：2016-06-14

申请号：US13983145

申请日：2011-02-08

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G11C5/14 ,  G06F1/32

CPC分类号： G11C5/14 ,  G06F1/3225 ,  G06F1/3275 ,  Y02D10/14 ,  Y02D50/20

摘要： An integrated circuit device comprising at least one memory module comprising a plurality of memory sub-modules, and at least one power management module arranged to provide power management for the at least one memory module. The at least one power management module is arranged to determine when content of at least one memory sub-module is redundant, and place the at least one memory sub-module into a powered-down state upon determining that content of the at least one memory sub-module is redundant.

摘要翻译： 一种集成电路装置，包括至少一个包括多个存储器子模块的存储器模块，以及至少一个功率管理模块，被布置成为所述至少一个存储器模块提供功率管理。 所述至少一个电源管理模块被布置成确定至少一个存储器子模块的内容何时是冗余的，并且在确定所述至少一个存储器的内容之后将所述至少一个存储器子模块置于掉电状态 子模块是多余的。

公开(公告)号：US09354645B2

公开(公告)日：2016-05-31

申请号：US14115223

申请日：2011-05-27

申请人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

发明人： Michael Priel ,  Dan Kuzmin ,  Sergey Sofer

IPC分类号： G05F1/56 ,  G05F1/46 ,  G05F1/563 ,  H02M1/00

CPC分类号： G05F1/468 ,  G05F1/465 ,  G05F1/56 ,  G05F1/563 ,  H02M2001/0025 ,  Y10T307/406

摘要： A voltage regulating circuit is provided for regulating an output voltage in order to minimize an absolute difference between a level of said output voltage and a reference level. The voltage regulating circuit comprises a voltage regulator and a reference level generator. The reference level generator generates an internal reference level on the basis of said output voltage level and said reference level such that said internal reference level does not exceed said output voltage level by more than a maximum allowed increment. The voltage regulator regulates said output voltage in order to minimize an absolute difference between said output voltage level and said internal reference level. A method of regulating an output voltage is also disclosed.

摘要翻译： 提供电压调节电路，用于调节输出电压，以使所述输出电压的电平和参考电平之间的绝对差最小化。 电压调节电路包括电压调节器和参考电平发生器。 参考电平发生器基于所述输出电压电平和所述参考电平产生内部参考电平，使得所述内部参考电平不超过所述输出电压电平超过允许的最大增量。 电压调节器调节所述输出电压，以便最小化所述输出电压电平和所述内部参考电平之间的绝对差。 还公开了一种调节输出电压的方法。

公开(公告)号：US20150276869A1

公开(公告)日：2015-10-01

申请号：US14438234

申请日：2012-10-30

申请人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL

发明人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

IPC分类号： G01R31/3177 ,  G01R31/3185

摘要： There is provided an integrated circuit comprising at least one logic path, comprising a plurality of sequential logic elements operably coupled into a scan chain to form at least one scan chain under test, at least one IR drop sensor operably coupled to the integrated circuit power supply, operable to output a first logic state when a sensed supply voltage is below a first predefined value and to output a second logic state when the sensed supply voltage is above the first predefined value, at least one memory buffer operably coupled to a scan test data load-in input and a scan test data output of the at least one scan chain under test, and control logic operable to gate logic activity including the scan shift operation inside the integrated circuit for a single cycle when the at least one IR drop sensor outputs the first logic state and to allow normal scan test flow when the at least one IR drop sensor outputs the second logic state. There is also provided an associated method of performing at-speed scan testing of an integrated circuit.

摘要翻译： 提供了包括至少一个逻辑路径的集成电路，其包括可操作地耦合到扫描链中以形成至少一个待测扫描链的多个顺序逻辑元件，至少一个IR压降传感器，可操作地耦合到集成电路电源 ，当所感测的电源电压低于第一预定义值时，可操作以输出第一逻辑状态，并且当感测到的电源电压高于第一预定值时输出第二逻辑状态，至少一个存储器缓冲器可操作地耦合到扫描测试数据 负载输入和待测试的至少一个扫描链的扫描测试数据输出，以及当所述至少一个IR下降传感器输出时，控制逻辑可操作以对包含集成电路内的扫描移位操作的门逻辑活动进行单个周期 所述第一逻辑状态并且当所述至少一个IR下降传感器输出所述第二逻辑状态时允许正常的扫描测试流程。 还提供了执行集成电路的高速扫描测试的相关方法。

公开(公告)号：US20150247899A1

公开(公告)日：2015-09-03

申请号：US14431794

申请日：2012-09-27

申请人： Sergey SOFER ,  Asher BERKOVITZ ,  Michael PRIEL ,  FREESCALE SEMICONDUCTOR, INC.

发明人： Sergey Sofer ,  Asher Berkovitz ,  Michael Priel

IPC分类号： G01R31/3185

CPC分类号： G01R31/318544 ,  G01R31/318575

摘要： A method generates scan patterns for testing an electronic device called DUT having a scan path. A scan tester is arranged for executing a scan shift mode and a capture mode. A scan test interface has a clock control unit for stretching a shift cycle of the scan clock in dependence of a scan clock pattern. The method determines at least one power shift cycle which is expected to cause a voltage drop of a supply voltage exceeding a predetermined threshold during respective shift cycles of the scan shift mode, and generates, in addition to the scan pattern, a scan clock pattern indicative of stretching the power shift cycle. Advantageously, a relatively high scan shift frequency may be used while avoiding detrimental effects of said voltage drop by extending the respective power shift cycle, whereby test time and yield loss are reduced.

摘要翻译： 一种方法产生用于测试具有扫描路径的称为DUT的电子设备的扫描模式。 扫描测试器被布置用于执行扫描移位模式和捕获模式。 扫描测试接口具有时钟控制单元，用于根据扫描时钟模式拉伸扫描时钟的移位周期。 该方法确定在扫描移位模式的相应移位周期期间期望导致电源电压超过预定阈值的电压降的至少一个功率偏移周期，并且除了扫描模式之外还产生指示的扫描时钟模式 拉伸动力换档循环。 有利地，可以使用相对高的扫描偏移频率，同时通过扩展相应的功率偏移周期来避免所述电压降的不利影响，从而降低测试时间和产量损失。

公开(公告)号：US20150206559A1

公开(公告)日：2015-07-23

申请号：US14415153

申请日：2012-07-20

申请人： Michael Priel ,  Leonid Fleshel ,  Dan Kuzmin

发明人： Michael Priel ,  Leonid Fleshel ,  Dan Kuzmin

IPC分类号： G11C7/10 ,  G11C7/06

CPC分类号： G11C7/1072 ,  G11C7/065 ,  G11C7/1039 ,  G11C7/22 ,  G11C19/00 ,  G11C19/28 ,  G11C29/32 ,  G11C2207/007

摘要： A register file module comprising at least one register array comprising a plurality of latch devices is described. The plurality of latch devices is arranged to individually provide memory bit-cells when the register file module is configured to operate in a first, functional operating mode, and at least one clock control component is arranged to receive a clock signal and to propagate the clock signal to the latch devices within the at least one register array. The register file module is configurable to operate in a second, scan mode in which the latch devices within the at least one register array are arranged into at least one scan chain. The at least one clock control component is arranged to propagate the clock signal to the latch devices within the at least one register array such that alternate latch devices within the at least one scan chain receive an inverted form of the clock signal.

摘要翻译： 描述了包括至少一个包括多个锁存装置的寄存器阵列的寄存器文件模块。 多个锁存装置被布置为当寄存器文件模块被配置为在第一功能操作模式下操作时，分别提供存储器位单元，并且至少一个时钟控制部件被布置成接收时钟信号并传播时钟 信号到至少一个寄存器阵列内的锁存器件。 寄存器文件模块可配置为以第二扫描模式操作，其中至少一个寄存器阵列内的锁存器件被布置成至少一个扫描链。 所述至少一个时钟控制部件布置成将所述时钟信号传播到所述至少一个寄存器阵列内的锁存器件，使得所述至少一个扫描链内的另外的锁存器件接收所述时钟信号的反相形式。

公开(公告)号：US20150204917A1

公开(公告)日：2015-07-23

申请号：US14415151

申请日：2012-07-19

申请人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

发明人： Michael Priel ,  Leonid Fleshel ,  Sergey Sofer

IPC分类号： G01R19/10 ,  G01R31/28

CPC分类号： G01R19/10 ,  G01R31/2856

摘要： A system for on-die voltage difference measurement on a pass device comprises a first voltage controlled oscillator circuit having a first voltage control input connectable to a first terminal of the pass device; a second voltage controlled oscillator circuit having a second voltage control input connectable to a second terminal of the pass device; a first counter circuit arranged to count oscillation periods of a first output signal from the first voltage controlled oscillator circuit and to provide a stop signal when a predefined number of the oscillation periods of the first output signal is counted; and a second counter circuit arranged to count oscillation periods of a second output signal from the second voltage controlled oscillator circuit and to stop counting depending on the stop signal.

摘要翻译： 用于通过装置上的片上电压差测量的系统包括：第一压控振荡器电路，具有可连接到通过装置的第一端子的第一电压控制输入; 第二压控振荡器电路，具有可连接到通过装置的第二端子的第二电压控制输入; 第一计数器电路，被布置成对来自第一压控振荡器电路的第一输出信号的振荡周期进行计数，并且当计数第一输出信号的预定数量的振荡周期时提供停止信号; 以及第二计数器电路，被布置成对来自第二压控振荡器电路的第二输出信号的振荡周期进行计数，并根据停止信号停止计数。