公开(公告)号：US20060001479A1

公开(公告)日：2006-01-05

申请号：US10882512

申请日：2004-06-30

申请人： Gerald Barkley ,  Mase Taub

发明人： Gerald Barkley ,  Mase Taub

IPC分类号： H02J1/00

CPC分类号： G11C16/30 ,  G05F3/205

摘要： Methods and apparatuses associated with providing a bias voltage for an n-type and a p-type device. A high voltage may be received and used to derive a bias voltage that would reduce a risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in an n-type device. The high voltage may be used to derive a bias voltage that would reduce the risk of gate-aided breakdown of the drain-to-substrate channel-side pn-junction in a p-type device.

摘要翻译： 与提供n型和p型装置的偏置电压有关的方法和装置。 可以接收高电压并用于导出偏置电压，这将降低n型器件中漏极到衬底沟道侧pn结的栅极辅助击穿的风险。 可以使用高电压来导出偏压，这将降低p型器件中漏极到衬底沟道侧pn结的栅极辅助击穿的风险。

公开(公告)号：US07623373B2

公开(公告)日：2009-11-24

申请号：US11639092

申请日：2006-12-14

申请人： Gerald Barkley

发明人： Gerald Barkley

IPC分类号： G11C16/04

CPC分类号： G11C11/5642 ,  G11C16/08 ,  G11C16/28 ,  G11C16/30

摘要： The delay arising from wordline capacitance in multi-level memories may be reduced by adding switched transistors along the wordline path. Also, the wordline may be pre-charged to a high level and then the first wordline voltage level for reading may be a center level. The switched transistors may be p-devices whose n-wells are biased by a stable DC voltage. Nodes along the wordline may float when not accessed. Finally, a distributed voltage generator may be used.

摘要翻译： 通过沿着字线路径添加开关晶体管，可以减少由多电平存储器中的字线电容产生的延迟。 此外，字线可以被预先充电到高电平，然后用于读取的第一字线电压电平可以是中心电平。 开关晶体管可以是其n阱被稳定的DC电压偏置的p器件。 当不被访问时，字线上的节点可能会浮动。 最后，可以使用分布式电压发生器。

公开(公告)号：US07525865B2

公开(公告)日：2009-04-28

申请号：US11771582

申请日：2007-06-29

申请人： Bharat Chauhan ,  Gerald Barkley ,  Kerry D. Tedrow ,  Balaji Sivakumar

发明人： Bharat Chauhan ,  Gerald Barkley ,  Kerry D. Tedrow ,  Balaji Sivakumar

IPC分类号： G11C5/14

CPC分类号： G11C5/14 ,  G11C16/30

摘要： Disclosed is a method for refreshing voltages in a non volatile memory during a standby mode. The method comprises generating a first node voltage and a second node voltage through a resistance ladder, storing the voltages in a pair of capacitors, comparing the voltages by a comparator, generating an output electrical signal by the comparator upon comparing the voltages, latching the output electrical signal by a flip flop, generating an electrical refresh pulse by a refresh pulse generator upon receiving the output electrical signal from the flip flop, the electrical refresh pulse being supplied to a refresh node of a plurality of refresh nodes in the non volatile memory and generating an electrical sample pulse by a sample pulse generator, the electrical sample pulse along with the electrical refresh pulse setting the flip flop, thereby causing the flip flop to latch a new output electrical signal.

摘要翻译： 公开了一种在待机模式期间刷新非易失性存储器中的电压的方法。 该方法包括通过电阻梯形生成第一节点电压和第二节点电压，将电压存储在一对电容器中，通过比较器比较电压，在比较电压时产生比较器的输出电信号，锁存输出 通过触发器产生电信号，当从触发器接收到输出电信号时，通过刷新脉冲发生器产生电刷新脉冲，电刷新脉冲被提供给非易失性存储器中的多个刷新节点的刷新节点， 通过采样脉冲发生器产生电采样脉冲，电采样脉冲与电刷新脉冲一起设置触发器，从而使触发器锁存新的输出电信号。

公开(公告)号：US20120263005A1

公开(公告)日：2012-10-18

申请号：US13085454

申请日：2011-04-12

申请人： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

发明人： Gerald Barkley ,  Efrem Bolandrina ,  Daniele Vimercati

IPC分类号： G11C8/10

CPC分类号： G11C8/10 ,  G11C5/025 ,  G11C8/14

摘要： A memory device includes wordline decoder circuits that share components between adjacent memory blocks. The wordline decoder circuits include multiple levels, where at least one level is split, driving half of the wordlines in one adjacent memory block and driving half of the wordlines in another adjacent memory block. Memory blocks have every other wordline coupled to one adjacent decoder circuit, and the remaining wordlines coupled to another adjacent decoder circuit.

摘要翻译： 存储器件包括在相邻存储器块之间共享组件的字线解码器电路。 字线解码器电路包括多个电平，其中至少一个电平被分离，驱动一个相邻存储器块中的一半字线并驱动另一相邻存储器块中的一半字线。 存储器块具有耦合到一个相邻解码器电路的每隔一个字线，并且剩余字线耦合到另一相邻解码器电路。

公开(公告)号：US08243497B1

公开(公告)日：2012-08-14

申请号：US12628153

申请日：2009-11-30

申请人： Fabio Pellizzer ,  Agostino Pirovano ,  Augusto Benvenuti ,  Daniele Vimercati ,  Andrea Redaelli ,  Gerald Barkley

发明人： Fabio Pellizzer ,  Agostino Pirovano ,  Augusto Benvenuti ,  Daniele Vimercati ,  Andrea Redaelli ,  Gerald Barkley

IPC分类号： G11C11/00

CPC分类号： G11C8/14 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0033 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2013/008 ,  G11C2213/79

摘要： A Phase Change Memory device with reduced programming disturbance and its operation are described. The Phase Change Memory includes an array with word lines and bit lines and voltage controlling elements coupled to bit lines adjacent to an addressed bit line to maintain the voltage of the adjacent bit lines within an allowed range.

摘要翻译： 描述了具有减少的编程干扰及其操作的相变存储器件。 相变存储器包括具有字线和位线的阵列，以及耦合到与寻址位线相邻的位线的电压控制元件，以将相邻位线的电压维持在允许的范围内。

公开(公告)号：US07518932B2

公开(公告)日：2009-04-14

申请号：US11644622

申请日：2006-12-22

申请人： Gerald Barkley ,  John Rudelic

发明人： Gerald Barkley ,  John Rudelic

IPC分类号： G11C11/34

CPC分类号： G11C16/349 ,  G06F12/0246

摘要： Erase cycle counting may be used for a non-volatile memory to balance the cycles on memory blocks or partitions. In some embodiments, the non-volatile memory may include two memory locations such as wordlines associated with each block of memory. The wordlines may be alternately erased so that an updated cycle count is transferred from the wordlines to the other. In the case of a power loss in the course of the updating of the cycle count, a method may detect that the data is in improper states and require that the erase be restarted after the power loss in order to recover the correct erase cycle count.

摘要翻译： 擦除周期计数可用于非易失性存储器以平衡存储器块或分区上的周期。 在一些实施例中，非易失性存储器可以包括两个存储器位置，例如与每个存储器块相关联的字线。 可以交替地擦除字线，使得更新的周期计数从字线传输到另一个。 在更新周期计数的过程中发生功率损耗的情况下，方法可以检测到数据处于不正确的状态，并要求在功率损耗之后重新启动擦除，以恢复正确的擦除周期计数。

公开(公告)号：US20080285339A1

公开(公告)日：2008-11-20

申请号：US11803362

申请日：2007-05-14

申请人： Gerald Barkley

发明人： Gerald Barkley

IPC分类号： G11C11/34 ,  G05F1/10

CPC分类号： G11C5/147 ,  G11C11/5642 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3431 ,  G11C27/024 ,  G11C2211/5634

摘要： A voltage reference generator includes multiple closed loop voltage references. Each of the closed loop voltage references uses a flash cell with a variable threshold voltage and a feedback loop to trim a reference voltage. The voltage reference generator includes sample and hold capacitors in output stages to allow reference voltages to be refreshed during a standby mode of operation.

摘要翻译： 电压参考发生器包括多个闭环电压基准。 每个闭环电压基准使用具有可变阈值电压的闪存单元和用于修整参考电压的反馈环路。 电压参考发生器包括在输出级中的采样和保持电容器，以允许在待机操作模式期间刷新参考电压。

公开(公告)号：US08804449B2

公开(公告)日：2014-08-12

申请号：US13605538

申请日：2012-09-06

申请人： Gerald Barkley ,  Nicholas Hendrickson

发明人： Gerald Barkley ,  Nicholas Hendrickson

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

摘要： An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

摘要翻译： 在一些实施方式中，诸如非易失性固态存储器件的装置可以包括存取线偏置电路，以响应于模式信息来设置与存储器芯的取消选择的存取线相关联的偏置电平。 在一种方法中，接入线偏置电路可以使用线性下调来改变存储器核心的取消选择的接入线路上的电压电平。 可以提供诸如主机处理器的存储器访问设备，其能够动态地设置存储器设备的存储器核心的操作模式，以便管理存储器的功耗。 还提供了其他装置和方法。

公开(公告)号：US20140064010A1

公开(公告)日：2014-03-06

申请号：US13605538

申请日：2012-09-06

申请人： Gerald Barkley ,  Nicholas Hendrickson

发明人： Gerald Barkley ,  Nicholas Hendrickson

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C5/14 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/004 ,  G11C13/0069 ,  G11C16/08 ,  G11C16/3427

摘要： An apparatus, such as a nonvolatile solid-state memory device, may, in some implementations, include access line bias circuitry to set a bias level associated with a deselected access line(s) of a memory core in response to mode information. In one approach, access line bias circuitry may use linear down regulation to change a voltage level on deselected access lines of a memory core. A memory access device, such as a host processor, may be provided that is capable of dynamically setting a mode of operation of a memory core of a memory device in order to manage power consumption of the memory. Other apparatuses and methods are also provided.

公开(公告)号：US08085584B1

公开(公告)日：2011-12-27

申请号：US12627214

申请日：2009-11-30

申请人： Poorna Kale ,  Greg Komoto ,  Gerald Barkley

发明人： Poorna Kale ,  Greg Komoto ,  Gerald Barkley

IPC分类号： G11C11/00

CPC分类号： G11C7/1006 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0069

摘要： Subject matter disclosed herein relates to user configuration of polarity of data storage in memory devices.

摘要翻译： 本文公开的主题涉及用户对存储器件中数据存储的极性的配置。