公开(公告)号：US06271562B1

公开(公告)日：2001-08-07

申请号：US09259636

申请日：1999-03-01

申请人： Gerald Deboy ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Heimo Graf

发明人： Gerald Deboy ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Heimo Graf

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/7395 ,  H01L29/7397 ,  H01L29/7813

摘要： A power semiconductor component that can be controlled by a field effect has a multiplicity of parallel-connected individual components disposed in cells, the cells are disposed tightly packed on a relatively small space in a cell array. Parallel-connected source zones of the cells have shadowed regions that in each case reduce an effective W/L channel ratio in the cells containing the shadowed regions. The invention has the advantage that because of the provision of the shadowed regions inside the source zones that are preferably undoped or at least doped much weaker than the source zones, the critical regions in the cell array with the highest current density are specifically moderated. Thus the current density in the current-carrying filament of the cell is more homogeneously distributed. This measure renders it possible to reduce the cell grid spacing of the cells in the cell array, or to reduce the forward resistance per unit area, and this leads simultaneously to a reduction in the power loss.

摘要翻译： 可以通过场效应来控制的功率半导体元件具有设置在单元中的多个并联连接的各个组件，这些单元被紧密地封装在单元阵列的较小空间上。 单元的平行连接的源区具有阴影区域，每个区域在每个情况下降低包含阴影区域的单元格中的有效W / L通道比。 本发明的优点在于，由于在源极区内设置优选未掺杂或至少掺杂得比源极区弱的阴影区域，所以具有最高电流密度的电池阵列中的临界区域被特别缓和。 因此，电池的载流灯丝中的电流密度更均匀分布。 该测量使得可以减小单元阵列中的单元格的单元格间距，或者减小每单位面积的正向电阻，并且这同时导致功率损耗的降低。

公开(公告)号：US06812524B2

公开(公告)日：2004-11-02

申请号：US10013999

申请日：2001-12-11

申请人： Dirk Ahlers ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Hans Weber ,  Gerald Deboy ,  Helmut Strack ,  Armin Willmeroth

发明人： Dirk Ahlers ,  Jens-Peer Stengl ,  Jenoe Tihanyi ,  Hans Weber ,  Gerald Deboy ,  Helmut Strack ,  Armin Willmeroth

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0634 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/7816

摘要： A semiconductor component includes first and second connection zones formed in a semiconductor body, a channel zone surrounding the second connection zone in the semiconductor body, and a drift path that is formed between the channel zone and the first connection zone and contains a compensation zone. The compensation zone has a complementary conduction type with respect to the drift zone and includes at least two segments. A distance between the two adjacent segments is chosen such that the punch-through voltage between these segments lies in a voltage range that corresponds to the voltage range assumed by the voltage drop across the drift path at currents situated between the rated current and twice the rated current.

摘要翻译： 半导体部件包括形成在半导体本体中的第一和第二连接区域，围绕半导体主体中的第二连接区域的沟道区域以及形成在沟道区域和第一连接区域之间并且包含补偿区域的漂移路径。 补偿区相对于漂移区具有互补导电类型并且包括至少两个段。 选择两个相邻段之间的距离，使得这些段之间的穿通电压位于对应于位于额定电流和额定电流两倍之间的电流处的漂移路径上的电压降所假定的电压范围的电压范围 当前。

公开(公告)号：US06870201B1

公开(公告)日：2005-03-22

申请号：US09530553

申请日：1998-11-02

申请人： Gerald Deboy ,  Jenoe Tihanyi ,  Helmut Strack ,  Helmut Gassel ,  Jens-Peer Stengl ,  Hans Weber

发明人： Gerald Deboy ,  Jenoe Tihanyi ,  Helmut Strack ,  Helmut Gassel ,  Jens-Peer Stengl ,  Hans Weber

IPC分类号： H01L29/06 ,  H01L29/417 ,  H01L29/739 ,  H01L29/78 ,  H01L29/74

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/41766 ,  H01L29/7395 ,  H01L29/7396 ,  H01L29/7802

摘要： The invention relates to a high voltage resistant edge structure in the edge region of a semiconductor component which has floating guard rings of the first conductivity type and inter-ring zones of the second conductivity type which are arranged between the floating guard rings, wherein the conductivities and/or the inter-ring zones are set such that their charge carriers are totally depleted when blocking voltage is applied. The inventive edge structure achieves a modulation of the electrical field both at the surface and in the volume of the semiconductor body. If the inventive edge structure is suitably dimensioned, the field intensity maximum can easily be situated in the depth; that is, in the region of the vertical p-n junction. Thus, a suitable edge construction which permits a “soft” leakage of the electrical field in the volume can always be provided over a wide range of concentrations of p and n doping.

摘要翻译： 本发明涉及一种半导体元件的边缘区域中的耐高压边缘结构，其具有布置在浮动保护环之间的第一导电类型的浮动保护环和第二导电类型的环形区，其中电导率 和/或环形区域被设置为使得当施加阻断电压时它们的电荷载流子完全耗尽。 本发明的边缘结构在半导体本体的表面和体积上实现了电场的调制。 如果本发明的边缘结构适当地确定尺寸，则场强度最大值可以容易地位于深度中; 也就是在垂直p-n结的区域。 因此，允许在体积中的电场的“软”泄漏的合适的边缘构造总是可以在宽泛的p和n掺杂浓度范围内提供。

公开(公告)号：US06831327B2

公开(公告)日：2004-12-14

申请号：US09838743

申请日：2001-04-19

申请人： Gerald Deboy ,  Jens-Peer Stengl ,  Hans Weber ,  Armin Willmeroth

发明人： Gerald Deboy ,  Jens-Peer Stengl ,  Hans Weber ,  Armin Willmeroth

IPC分类号： H01L2994

CPC分类号： H01L29/7802 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/7395 ,  H01L29/7811

摘要： A vertically structured semiconductor power component is described. A layer thickness of a substrate of the power module between a pn junction and a metallized back is chosen in such a manner that a space charge region produced in the semiconductor component extends as far as the back when a blocking voltage between a source and a drain electrode is applied before a field strength produced by the applied blocking voltage reaches a critical value.

摘要翻译： 描述了垂直结构的半导体功率部件。 选择在pn结和金属化反射层之间的功率模块的衬底的层厚度，使得当半导体组件中产生的空间电荷区域在源极和漏极之间的阻断电压 在施加的阻挡电压产生的场强达到临界值之前施加电极。

公开(公告)号：US06465863B1

公开(公告)日：2002-10-15

申请号：US09701527

申请日：2000-11-28

申请人： Gerald Deboy ,  Jens-Peer Stengl

发明人： Gerald Deboy ,  Jens-Peer Stengl

IPC分类号： H01L2358

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/744 ,  H01L29/861 ,  H01L2924/0002 ,  H01L2924/00

摘要： The invention relates to a power diode structure having improved dynamic characteristics which comprises a semiconductor body of a first conduction type. A semiconductor zone of the other conduction type which is contrary to the first conduction type is embedded in the one surface of said semiconductor body. The power diode also comprises an anode which contacts the semiconductor zone, and has a cathode which contacts the semiconductor body. At least one floating region of the second conduction type is provided in the semiconductor body.

摘要翻译： 本发明涉及具有改进的动态特性的功率二极管结构，其包括第一导电类型的半导体本体。 与第一导电类型相反的另一导电类型的半导体区域嵌入在所述半导体本体的一个表面中。 功率二极管还包括接触半导体区的阳极，并具有与半导体本体接触的阴极。 在半导体本体中设置有至少一个第二导电类型的浮动区域。

公开(公告)号：US6037631A

公开(公告)日：2000-03-14

申请号：US156429

申请日：1998-09-18

申请人： Gerald Deboy ,  Helmut Gassel ,  Jens-Peer Stengl

发明人： Gerald Deboy ,  Helmut Gassel ,  Jens-Peer Stengl

IPC分类号： H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417 ,  H01L29/78 ,  H01L29/94 ,  H01L29/749

CPC分类号： H01L29/7811 ,  H01L29/0696 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/41766

摘要： A semiconductor component having a high-voltage endurance edge structure in which a multiplicity of parallel-connected individual components are disposed in a multiplicity of cells of a cell array. In an edge region, the semiconductor component has cells with shaded source zone regions. During commutation of the power semiconductor component, the shaded source zone regions suppress the switching on of a parasitic bipolar transistor caused by the disproportionately large reverse flow current density. Moreover, an edge structure having shaded source zone regions can be produced very easily in technological terms, in particular in the case of self-adjusting processes, and can thus be produced cost-effectively.

摘要翻译： 一种具有高电压耐久性边缘结构的半导体元件，其中多个并联连接的各个部件被布置在电池阵列的多个单元中。 在边缘区域中，半导体部件具有带有阴影源区域区域的单元。 在功率半导体部件的换向期间，阴影源极区域抑制由不相当大的反向流动电流密度引起的寄生双极晶体管的导通。 此外，具有阴影源区区域的边缘结构可以在技术上非常容易地制造，特别是在自调整过程的情况下，因此可以成本有效地制造。

公开(公告)号：US06479876B1

公开(公告)日：2002-11-12

申请号：US09462759

申请日：2000-10-12

申请人： Gerald Deboy ,  Jenoe Tihanyi

发明人： Gerald Deboy ,  Jenoe Tihanyi

IPC分类号： H01L2976

CPC分类号： H01L29/7802 ,  H01L29/0634 ,  H01L29/167 ,  H01L29/32

摘要： The invention relates to a vertical power MOSFET having additional column-like zones (11, 12) which are arranged in an inner zone (1) and have the same and the opposite conductivity type as/to the inner zone (1). The charge carrier life is reduced in the additional zones (12), which are of the same conductivity type as the inner zone (1), and the inner zone (1) is dimensioned such that the space charge zone does not reach the junction between the inner zone and a drain zone.

摘要翻译： 本发明涉及具有附加的柱状区域（11,12）的垂直功率MOSFET，其布置在内部区域（1）中并且具有与内部区域（1）相同的导电类型。 在与内部区域（1）具有相同导电类型的附加区域（12）中减少电荷载体寿命，并且内部区域（1）的尺寸被设计成使得空间电荷区域不会到达 内部区域和排水区域。

公开(公告)号：US09484746B2

公开(公告)日：2016-11-01

申请号：US13352202

申请日：2012-01-17

申请人： Yi Tang ,  Gerald Deboy

发明人： Yi Tang ,  Gerald Deboy

IPC分类号： H02J1/00 ,  H02J3/38 ,  H02M7/5387 ,  H02M1/00

CPC分类号： H02J3/383 ,  H02M7/53871 ,  H02M2001/0074 ,  H02M2001/0077 ,  Y02E10/563 ,  Y10T307/707

摘要： A power converter circuit includes output terminals configured to receive an external AC voltage. At least one series circuit has at least two converter units. Each converter unit includes input terminals configured to be coupled to a DC power source. Output terminals provide an AC output current. The at least one series circuit is connected between the output terminals of the power converter circuit. A voltage measurement circuit is connected between the output terminals of the power converter circuit and configured to provide at least one measurement signal that includes information related to phase and frequency of the external AC voltage. At least one of the converter units is configured to receive the at least one measurement signal and is configured to regulate the generation of the AC output current dependent on the at least one measurement signal.

摘要翻译： 电源转换器电路包括被配置为接收外部AC电压的输出端子。 至少一个串联电路具有至少两个转换器单元。 每个转换器单元包括被配置为耦合到DC电源的输入端。 输出端子提供交流输出电流。 所述至少一个串联电路连接在所述电力转换器电路的输出端子之间。 电压测量电路连接在功率转换器电路的输出端之间，并被配置为提供至少一个测量信号，其包括与外部AC电压的相位和频率有关的信息。 所述转换器单元中的至少一个被配置为接收所述至少一个测量信号，并且被配置为根据所述至少一个测量信号来调节所述AC输出电流的产生。

公开(公告)号：US09478989B2

公开(公告)日：2016-10-25

申请号：US13440572

申请日：2012-04-05

申请人： Gerald Deboy ,  Yi Tang

发明人： Gerald Deboy ,  Yi Tang

IPC分类号： H02J1/00 ,  H02J3/38 ,  H02J3/40

CPC分类号： H02J3/385 ,  H02J3/387 ,  H02J3/40 ,  Y02E10/58 ,  Y10T307/707

摘要： A power converter circuit includes output terminals configured to receive an external voltage. A series circuit includes a number of converter units, each including input terminals configured to be coupled to a DC power source and output terminals configured to provide an output current. The series circuit is connected between the output terminals of the power converter circuit. A synchronization circuit is configured to generate a synchronization signal. The power converter circuit can be operated in a normal operation mode. In the normal operation mode, the synchronization circuit is configured to generate the synchronization signal dependent on the external voltage. In the normal operation mode, at least one converter unit of the plurality of converter units is configured to receive the synchronization signal and to regulate a generation of the output current such that a frequency and/or a phase of the output current is dependent on the synchronization signal.

摘要翻译： 电源转换器电路包括被配置为接收外部电压的输出端子。 串联电路包括多个转换器单元，每个转换器单元包括被配置为耦合到DC电源的输入端子和被配置为提供输出电流的输出端子。 串联电路连接在电源转换器电路的输出端子之间。 同步电路被配置为产生同步信号。 电源转换器电路可以在正常工作模式下工作。 在正常操作模式中，同步电路被配置为根据外部电压产生同步信号。 在正常操作模式中，多个转换器单元中的至少一个转换器单元被配置为接收同步信号并调节输出电流的产生，使得输出电流的频率和/或相位取决于 同步信号

公开(公告)号：US08829946B2

公开(公告)日：2014-09-09

申请号：US13597887

申请日：2012-08-29

申请人： Gerald Deboy ,  Karl Norling

发明人： Gerald Deboy ,  Karl Norling

IPC分类号： H03K3/00

CPC分类号： H03K17/166

摘要： One aspect is a circuit having an input configured to receive an input signal, and an actuation output configured to be connected to an actuation terminal of a transistor. A measurement arrangement is configured to ascertain at least one of a load current through a load path of the transistor, and a load voltage across the load path of the transistor and to provide a measurement signal that is dependent on at least one of the load current and the load path voltage. An actuation current source is configured to receive the measurement signal and to provide an actuation current at the actuation output, the actuation current having a current level dependent on the measurement signal.

摘要翻译： 一个方面是具有被配置为接收输入信号的输入的电路和被配置为连接到晶体管的致动端子的致动输出。 测量布置被配置为确定通过晶体管的负载路径的负载电流和跨越晶体管的负载路径的负载电压中的至少一个，并且提供取决于负载电流中的至少一个的测量信号 和负载路径电压。 致动电流源被配置为接收测量信号并且在致动输出处提供致动电流，所述致动电流具有取决于测量信号的电流水平。