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    Method of manufacturing a sag-resistant bonded particulate article
    4.
    发明授权
    Method of manufacturing a sag-resistant bonded particulate article 失效
    制造耐下沉粘合颗粒物品的方法

    公开(公告)号：US5013598A

    公开(公告)日：1991-05-07

    申请号：US546139

    申请日：1990-06-29

    申请人： Gerald J. Guerro ,  Balwant Singh

    发明人： Gerald J. Guerro ,  Balwant Singh

    IPC分类号： C08G12/20 ,  E04F13/16

    CPC分类号： E04F13/16 ,  C08G12/20 ,  Y10T442/2361 ,  Y10T442/2484

    摘要： A method for the production of improved bonded particulate articles, and the articles so produced, are disclosed. Specifically, the manufacture of particulate articles having a reduced tendency to undergo humidity-induced sag is disclosed. These articles have utility in such application as ceiling tiles.

    摘要翻译： 公开了一种制造改进的粘结微粒制品的方法以及如此制造的制品。 具体地，公开了具有减弱的湿度诱发下垂趋势的颗粒制品的制造。 这些文章在诸如天花板瓷砖的应用中具有实用性。

    Flexible on chip testing circuit for I/O's characterization
    5.
    发明授权
    Flexible on chip testing circuit for I/O's characterization 有权
    用于I / O表征的灵活的片上测试电路

    公开(公告)号：US07772833B2

    公开(公告)日：2010-08-10

    申请号：US12135418

    申请日：2008-06-09

    申请人： Narayanan Vijayaraghavan ,  Balwant Singh

    发明人： Narayanan Vijayaraghavan ,  Balwant Singh

    IPC分类号： G01R31/28

    CPC分类号： G01R31/31715

    摘要： The present invention provides a flexible on-chip testing circuit and methodology for measuring I/O characterization of multiple I/O structures. The testing circuit includes a register bank, a central processing controller (CPC), a character slew module, a delay characterization module, and a character frequency module. The register bank stores multiple instructions, and measurement results. The CPC fetches the instructions from the register bank. The CPC includes various primary and secondary state machines for interpreting the fetched instructions for execution. Depending on the input instruction the CPC applies stimulus to the IUT and the output of the IUT is used by the Local characterization modules (CHARMODULE) to extract the desired characterization parameters such as the character slew module which measures a voltage rise/fall time either for a single voltage IUT or a multi-voltage IUT. The Test Methodology for STIOBISC consists of an automated ATE pattern generation from verification test benches and automated result processing by converting the ATE data logs into the final readable format, thereby considerably reducing the test setup and output processing time. The testing circuit can operate in multiple modes for selecting one of these modules.

    摘要翻译： 本发明提供了用于测量多个I / O结构的I / O表征的灵活的片上测试电路和方法。 测试电路包括寄存器组，中央处理控制器（CPC），字符转换模块，延迟表征模块和字符频率模块。 注册银行存储多个指令和测量结果。 CPC从注册银行取得指示。 CPC包括用于解释获取的指令执行的各种主要和次要状态机。 根据输入指令，CPC对IUT应用激励，IUT的输出由本地表征模块（CHARMODULE）用于提取所需的特性参数，例如测量电压上升/下降时间的字符转换模块， 单电压IUT或多电压IUT。 STIOBISC的测试方法包括通过将ATE数据日志转换为最终可读格式的验证测试台和自动化结果处理的自动ATE模式生成，从而大大降低了测试设置和输出处理时间。 测试电路可以在多种模式下工作，以选择这些模块之一。

    Resolution in measuring the pulse width of digital signals
    6.
    发明授权
    Resolution in measuring the pulse width of digital signals 有权
    分辨率测量数字信号的脉冲宽度

    公开(公告)号：US07516032B2

    公开(公告)日：2009-04-07

    申请号：US10327705

    申请日：2002-12-20

    申请人： Balwant Singh

    发明人： Balwant Singh

    IPC分类号： G06F19/00 ,  G01R29/02 ,  G01R25/08

    CPC分类号： G01R31/2882 ,  G01R29/02 ,  G01R31/3016 ,  G01R31/31937

    摘要： A system and method for providing improved resolution in the measuring the pulse width of digital signals comprising counting the integral number of measuring clock pulses covered by said digital pulse and triggering a chain of cascaded high resolution delay elements from the trailing edge of said measuring clock pulses. Further, the invention measures the delay count obtained from said chain of cascaded delay elements from the trailing edge of the last measuring clock pulse up to the end of said digital pulse, and adds said measured delay count to said integral measuring clock pulse count to obtain the total width of said digital pulse.

    摘要翻译： 一种用于在测量数字信号的脉冲宽度时提供改进的分辨率的系统和方法，包括对由所述数字脉冲覆盖的测量时钟脉冲的整数进行计数，并从所述测量时钟脉冲的后沿触发级联的高分辨率延迟元件链 。 此外，本发明还测量从所述最后测量时钟脉冲的后沿到所述数字脉冲的末端从所述级联延迟元件链获得的延迟计数，并将所述测量的延迟计数加到所述积分测量时钟脉冲计数以获得 所述数字脉冲的总宽度。

    Configurable length first-in first-out memory
    7.
    发明申请
    Configurable length first-in first-out memory 有权
    可配置长度先进先出存储器

    公开(公告)号：US20060256636A1

    公开(公告)日：2006-11-16

    申请号：US11394874

    申请日：2006-03-31

    申请人： Swapnil Bahl ,  Balwant Singh

    发明人： Swapnil Bahl ,  Balwant Singh

    IPC分类号： G11C7/00

    CPC分类号： G06F5/10 ,  G06F2205/063

    摘要： A configurable length first-in first-out (FIFO) memory includes a memory core for storing data, a write address counter connected to the memory core for counting locations for writing the data to be stored, and a read address counter connected to the memory core for counting the locations for reading the stored data. The read address counter includes a comparator for generating a synchronous reset for itself. A selector is connected to the comparator for selecting a user defined FIFO length, or a pre-programmed write address counter length.

    摘要翻译： 可配置长度先进先出（FIFO）存储器包括用于存储数据的存储器核心，连接到存储器核心的写地址计数器，用于计数用于写入要存储的数据的位置，以及连接到存储器的读地址计数器 用于计数读取存储数据的位置的核心。 读地址计数器包括用于自身产生同步复位的比较器。 选择器连接到比较器，用于选择用户定义的FIFO长度，或预编程的写入地址计数器长度。