公开(公告)号：US06772328B1

公开(公告)日：2004-08-03

申请号：US09335939

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

发明人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

IPC分类号： G06F15177

CPC分类号： G06F13/4068

摘要： In a common processor module/motherboard interface, an interface protocol is defined such that a replacement processor module can be recognized by a common motherboard and such that a common processor module can be compatible with multiple motherboards. A module information field stored on a processor module includes status information pertaining to the processor module. When the processor module is coupled to a motherboard, the motherboard downloads the module information field and generates initialization commands for the processor module based on the retrieved module information field. The commands are transferred to the processor module for initialization of the processor.

摘要翻译： 在通常的处理器模块/主板接口中，定义了一个接口协议，使得替换处理器模块可以被公共主板识别，并且使公共处理器模块可以与多个主板兼容。 存储在处理器模块上的模块信息字段包括与处理器模块有关的状态信息。 当处理器模块耦合到母板时，主板下载模块信息字段，并且基于检索的模块信息字段为处理器模块生成初始化命令。 这些命令被传送到处理器模块，用于处理器的初始化。

公开(公告)号：US06516373B1

公开(公告)日：2003-02-04

申请号：US09335954

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

发明人： Gerald Talbot ,  Hanwoo Cho ,  Eric Rowe

IPC分类号： G06F1300

CPC分类号： G06F13/4068

摘要： A common motherboard interface accommodates processor modules of different processor architectures. The system comprises an interface for communicating with a processor module inserted at the motherboard. The interface receives an identifier signal from the processor module. The identifier signal identifies the processor module architecture. An architecture selection circuit selectively exchanges processor architecture specific signals with the processor module based on the identifier signal. In this manner, a multiple of processor modules of completely different processor architectures can share a common motherboard, thereby providing a system that can be field-upgraded by processor modules of different architectures, or simply allowing the same motherboard to be employed in two different products of different processor architectures.

摘要翻译： 通用的主板接口可容纳不同处理器架构的处理器模块。 该系统包括用于与插入主板的处理器模块通信的接口。 该接口从处理器模块接收标识符信号。 标识符信号标识处理器模块体系结构。 架构选择电路基于标识符信号选择性地与处理器模块交换处理器架构特定信号。 以这种方式，具有完全不同的处理器架构的多个处理器模块可以共享公共主板，从而提供可以由不同架构的处理器模块进行现场升级的系统，或者简单地允许将相同的主板用于两种不同的产品 的不同处理器架构。

公开(公告)号：US06865682B1

公开(公告)日：2005-03-08

申请号：US09335940

申请日：1999-06-18

申请人： Gerald Talbot ,  Hanwoo Cho

发明人： Gerald Talbot ,  Hanwoo Cho

IPC分类号： G06F1/26 ,  H05K1/02 ,  H05K1/14 ,  G05F1/02 ,  G06F13/00

CPC分类号： G06F1/26 ,  H05K1/0254 ,  H05K1/141

摘要： In a microprocessor module assembly, voltage regulators are integrated into the module and adapted for use with a processor and support electronics likewise mounted on the module. The voltage regulators receive a fixed imput voltage from a motherboard interface and provide modified regulated output voltages to the processor and support electronics. In this manner, the processor module is readily upgradable such that future generations are compatible with a fixed motherboard interface without the need for upgrading voltage regulators on the motherboard. In a preferred embodiment, bulk decoupling capacitance is provided on the processor assembly to stabilize the DC output voltage of the voltage regulators.

摘要翻译： 在微处理器模块组件中，电压调节器集成到模块中并适用于同样安装在模块上的处理器和支撑电子装置。 电压调节器从主板接口接收固定的输入电压，并向处理器和支持电子设备提供修改的稳压输出电压。 以这种方式，处理器模块易于升级，使得后代与固定的主板接口兼容，而不需要升级主板上的稳压器。 在优选实施例中，体解耦电容被提供在处理器组件上以稳定稳压器的DC输出电压。

公开(公告)号：US08356155B2

公开(公告)日：2013-01-15

申请号：US12910412

申请日：2010-10-22

申请人： Shawn Searles ,  Nicholas T. Humphries ,  Brian W. Amick ,  Richard W. Reeves ,  Hanwoo Cho ,  Ronald L. Pettyjohn

发明人： Shawn Searles ,  Nicholas T. Humphries ,  Brian W. Amick ,  Richard W. Reeves ,  Hanwoo Cho ,  Ronald L. Pettyjohn

IPC分类号： G06F12/00

CPC分类号： G06F12/00 ,  G06F1/3275 ,  G06F13/1689 ,  G06F13/4072 ,  G06F13/4086 ,  Y02D10/14

摘要： A physical memory interface (Phy) and method of operating is disclosed. The Phy interface includes command and status registers (CSRs) configured to receive a first power context and second power context. Selection circuitry is configured to switch between the first and second power contexts. A plurality of adjustable delay elements are provided, each having a delay time responsive to the selected power context. A first set of CSRs configured may store the first power context and a second set of CSRs configured may store the second power context. The Phy interface may also include a plurality of drivers each having a selectable drive strength responsive to the selected power context. The Phy interface may also include a plurality of receivers each having a selectable termination impedance responsive to the selected power context. Switching between power contexts may result in adjusting of the delay elements, drive strength and/or termination impedance of one or more drivers/receivers.

摘要翻译： 公开了物理存储器接口（Phy）和操作方法。 Phy接口包括被配置为接收第一功率上下文和第二功率上下文的命令和状态寄存器（CSR）。 选择电路被配置为在第一和第二电源上下文之间切换。 提供了多个可调延迟元件，每个延迟元件具有响应于所选功率上下文的延迟时间。 配置的第一组CSR可以存储第一功率上下文，并且配置的第二组CSR可以存储第二功率上下文。 Phy接口还可以包括多个驱动器，每个驱动器响应于所选择的功率上下文具有可选择的驱动强度。 Phy接口还可以包括多个接收器，每个接收器具有响应于所选择的功率上下文的可选择的终端阻抗。 在功率上下文之间切换可导致延迟元件的调整，一个或多个驱动器/接收器的驱动强度和/或终端阻抗。

公开(公告)号：US08880831B2

公开(公告)日：2014-11-04

申请号：US13106285

申请日：2011-05-12

申请人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

发明人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

IPC分类号： G06F13/16

CPC分类号： G06F13/1663 ,  G06F13/1689

摘要： A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

摘要翻译： 公开了一种用于训练存储器的读延迟的方法和装置。 存储器控制器包括被配置为将命令传送到存储器的命令FIFO，耦合以从存储器接收数据的数据队列，以及配置为提供表示数据有效的第一时钟信号的周期数的寄存器 。 在启动程序期间，存储器控制器被配置为在经过第一时钟信号的指定数量的周期之后，将由数据队列接收的数据与已知数据模式进行比较。 存储器控制器还被配置为递减第一值，并且如果接收的数据与数据模式匹配，则重复传送和比较。 如果接收的数据与存储器的任何尝试读取的数据模式不匹配，则存储器控制器被配置为将第二值编程到寄存器中。

公开(公告)号：US20120290800A1

公开(公告)日：2012-11-15

申请号：US13106285

申请日：2011-05-12

申请人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

发明人： Guhan Krishnan ,  Jonathan M. Owen ,  Brian Amick ,  Hanwoo Cho

IPC分类号： G06F12/02

CPC分类号： G06F13/1663 ,  G06F13/1689

摘要： A method and apparatus for training read latency of a memory are disclosed. A memory controller includes a command FIFO configured to convey commands to a memory, a data queue coupled to receive data from the memory, and a register configured to provide a value indicative of a number of cycles of a first clock signal after which data is valid. During a startup routine, the memory controller is configured to compare data received by the data queue to a known data pattern after a specified number of cycles of the first clock signal have elapsed. The memory controller is further to configured to decrement the first value and repeat conveying and comparing if the data received matches the data pattern. If the received data does not match the data pattern for any attempted read of the memory, the memory controller is configured to program a second value into the register.

摘要翻译： 公开了一种用于训练存储器的读延迟的方法和装置。 存储器控制器包括被配置为将命令传送到存储器的命令FIFO，耦合以从存储器接收数据的数据队列，以及配置为提供表示数据有效的第一时钟信号的周期数的寄存器 。 在启动程序期间，存储器控制器被配置为在经过第一时钟信号的指定数量的周期之后，将由数据队列接收的数据与已知数据模式进行比较。 存储器控制器还被配置为递减第一值，并且如果接收的数据与数据模式匹配，则重复传送和比较。 如果接收的数据与存储器的任何尝试读取的数据模式不匹配，则存储器控制器被配置为将第二值编程到寄存器中。

公开(公告)号：US20120159271A1

公开(公告)日：2012-06-21

申请号：US12972977

申请日：2010-12-20

申请人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

发明人： Hanwoo Cho ,  Tahsin Askar ,  Philip E. Madrid ,  Guhan Krishnan ,  Brian W. Amick ,  Shawn Searles ,  Ryan J. Hensley

IPC分类号： G06F11/263

CPC分类号： G11C29/1201 ,  G11C29/022

摘要： A memory loopback system and method including an address/command transmit source configured to transmit a command and associated address through an address/command path. A transmit data source is configured to transmit write data associated with the command through a write path. Test control logic is configured to generate gaps between successive commands. A loopback connection is configured to route the write data from the write path to a read path. A data comparator is configured to compare the data received via the read path to a receive data source and generate a data loopback status output. Pattern generation logic can be configured to generate a loopback strobe, the loopback strobe being coupled to the read path. The pattern generation logic may be configured to synthesize a read strobe based on the test control logic and to use the synthesized read strobe as the loopback strobe. The loopback connection may be configured to route the address/command data from the address/command path to an address/command comparator, the address/command comparator being configured to compare the address/command data to an address/command receive source and generate an address/command loopback status output.

摘要翻译： 一种存储器环回系统和方法，包括地址/命令发送源，其被配置为通过地址/命令路径发送命令和相关联的地址。 发送数据源被配置为通过写入路径发送与该命令相关联的写入数据。 测试控制逻辑被配置为在连续命令之间产生间隙。 配置环回连接将写入数据从写入路径路由到读取路径。 数据比较器被配置为将经由读取路径接收的数据与接收数据源进行比较，并生成数据环回状态输出。 模式生成逻辑可被配置为生成环回选通，环回选通被耦合到读取路径。 图案生成逻辑可以被配置为基于测试控制逻辑来合成读选通脉冲，并且使用合成的读选通作为环回选通。 环回连接可以被配置为将地址/命令数据从地址/命令路径路由到地址/命令比较器，地址/命令比较器被配置为将地址/命令数据与地址/命令接收源进行比较，并生成 地址/命令环回状态输出。

公开(公告)号：US20090235108A1

公开(公告)日：2009-09-17

申请号：US12045916

申请日：2008-03-11

申请人： Spencer M. Gold ,  Alex Branover ,  Hanwoo Cho ,  Sebastien Nussbaum

发明人： Spencer M. Gold ,  Alex Branover ,  Hanwoo Cho ,  Sebastien Nussbaum

IPC分类号： G06F1/00

CPC分类号： G06F1/206 ,  G06F1/3203 ,  G06F1/324 ,  Y02D10/126

摘要： Processor overclocking techniques are disclosed. Upon automatically determining that overclocking entry criteria are satisfied, one or more cores are clocked above their standard operation frequencies. The cores may be overclocked until one or more exit criteria are satisfied. At that point, an exit procedure is performed, with the one or more overclocked cores return to their normal operating frequency.

摘要翻译： 处理器超频技术被公开。 当自动确定超频进入条件得到满足时，一个或多个核心的时钟频率超过其标准工作频率。 核心可以超频，直到满足一个或多个退出标准。 此时，执行一个退出程序，一个或多个超频核心恢复到正常工作频率。

公开(公告)号：US07234015B1

公开(公告)日：2007-06-19

申请号：US11151316

申请日：2005-06-14

申请人： Hanwoo Cho ,  Richard W. Reeves ,  Jelena Ilic

发明人： Hanwoo Cho ,  Richard W. Reeves ,  Jelena Ilic

IPC分类号： G06F13/00 ,  G06F13/36

CPC分类号： G06F13/4072

摘要： A method is provided for selectively using a PCIXCAP pin input to detect PCI/PCI-X bus mode or as DC pin input. The method provides a PCI/PCI-X device having PCIXCAP pin input, and a circuit having a plurality of voltage level detection structures and an output corresponding to each voltage level detection structure. Each output is received by a first logic to detect the PCI bus mode of a device defining a first, PCIXCAP mode for the pin input. The method ensures that one of the plurality of voltage level detection structures may be used as a DC signal logic to provide a DC output signal to a second logic. A mode of the PCIXCAP pin input is selected so as to provide the DC output signal under conditions where the PCI/PCI-X bus mode is not being detected. In an embodiment, the DC output signal is used in as a PCI Hot-Plug interface signal.

摘要翻译： 提供了一种选择性地使用PCIXCAP引脚输入来检测PCI / PCI-X总线模式或作为DC引脚输入的方法。 该方法提供具有PCIXCAP引脚输入的PCI / PCI-X器件，以及具有多个电压电平检测结构的电路和对应于每个电压电平检测结构的输出。 每个输出由第一逻辑接收以检测定义用于引脚输入的第一PCIXCAP模式的器件的PCI总线模式。 该方法确保多个电压电平检测结构中的一个可以用作DC信号逻辑以向第二逻辑提供DC输出信号。 选择PCIXCAP引脚输入的模式，以便在未检测到PCI / PCI-X总线模式的条件下提供直流输出信号。 在一个实施例中，DC输出信号用作PCI热插拔接口信号。

公开(公告)号：US10384754B2

公开(公告)日：2019-08-20

申请号：US15811783

申请日：2017-11-14

申请人： Sangha Cho ,  Hanwoo Cho ,  Whang Cho

发明人： Sangha Cho ,  Hanwoo Cho ,  Whang Cho

IPC分类号： B63H5/125 ,  B63H25/02 ,  F16H1/02 ,  B63H1/08 ,  B63H23/28 ,  B63H23/34 ,  B63H11/00 ,  B63H21/20 ,  B63H21/17 ,  F16H1/22 ,  F16H37/06 ,  F16H7/02

摘要： An azimuth thruster system includes a pod configured to rotate relative the hull of the ship about an azimuthal axis of the pod, a propeller shaft extending from the pod and being configured to rotate relative to the pod about a central axis of the propeller shaft, an outer shaft disposed at least partially in the pod and configured to be driven by a first primary prime mover, an inner shaft disposed at least partially within the outer shaft and configured to be driven by a second primary prime mover, and a pod gear unit disposed within the pod and coupled to the outer shaft, the inner shaft, and the propeller shaft. The outer and inner shafts are configured to rotate at least one of the pod and the propeller shaft based on directions and magnitudes of the torques generated by the first and second primary prime movers.