公开(公告)号：US10937786B2

公开(公告)日：2021-03-02

申请号：US16134173

申请日：2018-09-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Ruilong Xie ,  Laertis Economikos

IPC: H01L21/00 ,  H01L27/088 ,  H01L29/08 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to gate cut structures and methods of manufacture. The structure includes: a plurality of gate structures comprising source and drain regions and sidewall spacers comprised of different dielectric materials; and contacts connecting to the source and drain regions and isolated from the gate structures by the different dielectric materials.

公开(公告)号：US10937693B2

公开(公告)日：2021-03-02

申请号：US16150026

申请日：2018-10-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Andreas Knorr ,  Haiting Wang ,  Hui Zang

IPC: H01L21/768 ,  H01L29/66 ,  H01L21/285 ,  H01L21/02

Abstract: At least one method, apparatus and system disclosed herein involves forming local interconnect regions during semiconductor device manufacturing. A plurality of fins are formed on a semiconductor substrate. A gate region is over a portion of the fins. A trench silicide (TS) region is formed adjacent a portion of the gate region. The TS region comprises a first TS metal feature and a second TS metal feature. A bi-layer self-aligned contact (SAC) cap is formed over a first portion of the TS region and electrically coupled to a portion of the gate region. A portion of the bi-layer SAC cap is removed to form a first void. A first local interconnect feature is formed in the first void.

公开(公告)号：US10886178B2

公开(公告)日：2021-01-05

申请号：US16109258

申请日：2018-08-22

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Tek Po Rinus Lee ,  Annie Levesque ,  Qun Gao ,  Hui Zang ,  Rishikesh Krishnan ,  Bharat Krishnan ,  Curtis Durfee

IPC: H01L29/167 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L23/532 ,  H01L21/02 ,  H01L29/40 ,  H01L23/535

Abstract: A device including a triple-layer EPI stack including SiGe, Ge, and Si, respectively, with Ga confined therein, and method of production thereof. Embodiments include an EPI stack including a SiGe layer, a Ge layer, and a Si layer over a plurality of fins, the EPI stack positioned between and over a portion of sidewall spacers, wherein the Si layer is a top layer capping the Ge layer, and wherein the Ge layer is a middle layer capping the SiGe layer underneath; and a Ga layer in a portion of the Ge layer between the SiGe layer and the Si layer.

公开(公告)号：US10833171B1

公开(公告)日：2020-11-10

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/76 ,  H01L31/062 ,  H01L31/113 ,  H01L29/66 ,  H01L27/108 ,  H01L27/088 ,  H01L21/8234

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US10825913B2

公开(公告)日：2020-11-03

申请号：US16144275

申请日：2018-09-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Ruilong Xie

IPC: H01L29/66 ,  H01L29/78 ,  H01L27/088 ,  H01L27/02 ,  H01L21/8234

Abstract: A method, apparatus, and manufacturing system are disclosed for a fin field effect transistor having a reduced parasitic capacitance between a gate and a source/drain contact. In one embodiment, we disclose a semiconductor device including first and second fins; an isolation structure between the fins; first and second metal gates; a first dielectric body under the first metal gate and on the substrate between the first fin and the second fin, wherein a top of the first dielectric body is below a top of the first metal gate; and a second dielectric body in the second metal gate and on the substrate between the first fin and the second fin, wherein a top of the second dielectric body is at or above a top of the second metal gate.

公开(公告)号：US10825910B1

公开(公告)日：2020-11-03

申请号：US16386545

申请日：2019-04-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui Zang ,  Shesh Mani Pandey

IPC: H01L29/82 ,  H01L29/423 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/321 ,  H01L29/78 ,  H01L29/06 ,  H01L21/768

Abstract: Structures for field effect-transistors and methods of forming field-effect transistors. A gate structure includes a gate electrode and a gate dielectric layer that are arranged between a first sidewall spacer and a second sidewall spacer. The gate structure has a top surface that is recessed relative to the first and second sidewall spacers. A gate cap is arranged over a section of the gate structure and over the first and sidewall spacers. The gate cap has a first section of a first width arranged over the section of the gate structure and a second section of a second width arranged over the section of the gate cap, the first sidewall spacer, and the second sidewall spacer. A dielectric liner is arranged between the gate cap and the gate structure, between the gate cap and the first sidewall spacer, and between the gate cap and the second sidewall spacer.

公开(公告)号：US20200335600A1

公开(公告)日：2020-10-22

申请号：US16385436

申请日：2019-04-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanping Shen ,  Jiehui Shu ,  Hui Zang

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L27/108

Abstract: Disclosed is a transistor that includes a sidewall spacer positioned adjacent a sidewall of a gate structure, wherein the sidewall spacer comprises a notch proximate the lower end and wherein the notch is defined by a substantially vertically oriented side surface and a substantially horizontally oriented upper surface. An epi cavity in the substrate includes a substantially vertically oriented cavity sidewall that is substantially vertically aligned with the substantially vertically oriented side surface of the notch and an epi semiconductor material positioned in the epi cavity and in the notch, wherein the epi semiconductor material contacts and engages the substantially vertically oriented side surface of the notch and the substantially horizontally oriented upper surface of the notch.

公开(公告)号：US10811409B2

公开(公告)日：2020-10-20

申请号：US16161620

申请日：2018-10-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Jiehui Shu ,  Hui Zang ,  Guowei Xu ,  Jian Gao

IPC: H01L27/088 ,  H01L29/66 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51 ,  H01L29/78

Abstract: Methods of manufacturing FinFETs including providing a precursor FinFET structure having a substrate with fins thereon, S/D junctions on fin tops, an STI layer on the substrate and between fins, a conformal first dielectric layer on the STI layer and S/D junctions, and a second dielectric layer on the first dielectric layer; forming a conformal third dielectric layer on the second dielectric layer and surfaces of the first dielectric layer located above the second dielectric layer; forming a fourth dielectric layer on the third dielectric layer such that third dielectric layer located between adjacent fins is exposed and such that third dielectric layer located above the adjacent fins is exposed; removing the exposed third dielectric layer and the first dielectric layer located thereunder, thereby exposing the S/D junctions; and forming a metal contact on the exposed S/D junctions and the exposed portion of the third dielectric layer between adjacent fins.

公开(公告)号：US10797049B2

公开(公告)日：2020-10-06

申请号：US16170117

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui Zang ,  Haiting Wang ,  Chung Foong Tan ,  Guowei Xu ,  Ruilong Xie ,  Scott H. Beasor ,  Liu Jiang

IPC: H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/51 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/78

Abstract: A FinFET structure having reduced effective capacitance and including a substrate having at least two fins thereon laterally spaced from one another, a metal gate over fin tops of the fins and between sidewalls of upper portions of the fins, source/drain regions in each fin on opposing sides of the metal gate, and a dielectric bar within the metal gate located between the sidewalls of the upper portions of the fins, the dielectric bar being laterally spaced away from the sidewalls of the upper portions of the fins within the metal gate.

公开(公告)号：US10784195B2

公开(公告)日：2020-09-22

申请号：US15959727

申请日：2018-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jiehui Shu ,  Xiaoqiang Zhang ,  Haizhou Yin ,  Moosung M. Chae ,  Jinping Liu ,  Hui Zang

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/525

Abstract: Interconnect structures and methods of fabricating an interconnect structure. A first interconnect and a second interconnect extend in a first direction in a interlayer dielectric layer and are spaced apart from each other. A third interconnect is arranged in the interlayer dielectric layer to connect the first interconnect with the second interconnect. The first interconnect and the second interconnect have a first width, and the third interconnect has a second width that is less than the first width.