公开(公告)号：US20140217467A1

公开(公告)日：2014-08-07

申请号：US13758225

申请日：2013-02-04

Applicant: GLOBALFOUNDRIES INC.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L21/02 ,  H01L29/12

CPC classification number: H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract translation: 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

公开(公告)号：US09368578B2

公开(公告)日：2016-06-14

申请号：US13758225

申请日：2013-02-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L29/66 ,  H01L29/12 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/092 ,  H01L27/12

CPC classification number: H01L29/12 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1207 ,  H01L27/1211

Abstract: Obtaining a structure comprised of first and second layers of a first semiconductor materials and a strain relief buffer (SRB) layer between the first and second layers, forming a sidewall spacer on the sidewalls of an opening in the second layer, and forming a third semiconductor material in the opening, wherein the first, second and third semiconductor materials are different. A device includes first and second layers of first and second semiconductor materials and an SRB layer positioned above the first layer. The second layer is positioned above a first portion of the SRB layer, a region of a third semiconductor material is in an opening in the second layer and above a second portion of the SRB layer, and an insulating material is positioned between the region comprised of the third semiconductor material and the second layer.

Abstract translation: 在第一和第二层之间获得由第一半导体材料的第一和第二层和应变释放缓冲层（SRB）层组成的结构，在第二层的开口的侧壁上形成侧壁间隔物，并形成第三半导体 所述开口中的材料，其中所述第一，第二和第三半导体材料是不同的。 一种器件包括第一和第二层第一和第二半导体材料以及位于第一层之上的SRB层。 第二层位于SRB层的第一部分之上，第三半导体材料的区域位于第二层的开口中并且位于SRB层的第二部分之上，并且绝缘材料位于由 第三半导体材料和第二层。

公开(公告)号：US09362277B2

公开(公告)日：2016-06-07

申请号：US14175827

申请日：2014-02-07

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L21/8238 ,  H01L21/205 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308

CPC classification number: H01L29/7848 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/30625 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L27/0924 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

Abstract translation: 公开了一种形成具有小占地面积的多值逻辑晶体管的方法和所得到的器件。 实施例包括在硅衬底上形成多个翅片，每个翅片用硬掩模覆盖; 用氧化物填充翅片和硬掩模之间的空间; 去除硬掩模并使每个翅片凹陷，在每个翅片上的氧化物中形成空腔; 在每个空腔中形成多个Si基层，其中Ge或C的百分比增加或掺杂剂浓度从底层到顶层的浓度降低; 执行CMP以平坦化到翅片的顶部; 将氧化物凹陷到具有等于每个Si基层的厚度的厚度的略微低于翅片顶部的深度; 以及在多个Si基层上形成高k栅极电介质和金属栅电极。

公开(公告)号：US08716156B1

公开(公告)日：2014-05-06

申请号：US13757069

申请日：2013-02-01

Applicant: GlobalFoundries Inc.

Inventor： Bartlomiej Jan Pawlak ,  Steven Bentley ,  Ajey Jacob

IPC: H01L21/31

CPC classification number: H01L21/823821 ,  H01L21/845 ,  H01L29/66795

Abstract: One illustrative method disclosed herein includes forming a mandrel structure above a semiconductor substrate, performing an oxidation process to oxidize at least a portion of the mandrel structure so as to thereby define oxidized regions on the mandrel structure, removing the oxidized regions to thereby defined a reduced thickness mandrel structure, forming a plurality of fins on the reduced thickness mandrel structure and performing an etching process to selectively remove at least a portion of the reduced thickness mandrel structure so as to thereby expose at least a portion of each of the fins.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底之上形成心轴结构，执行氧化过程以氧化心轴结构的至少一部分，从而在心轴结构上限定氧化区，去除氧化区，由此限定减少 厚度心轴结构，在厚度较小的心轴结构上形成多个翅片，并执行蚀刻工艺以选择性地移除至少一部分厚度较小的心轴结构，从而露出每个翅片的至少一部分。

公开(公告)号：US10756213B2

公开(公告)日：2020-08-25

申请号：US16433626

申请日：2019-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L29/10 ,  H01L29/66 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.

公开(公告)号：US10388790B2

公开(公告)日：2019-08-20

申请号：US15082103

申请日：2016-03-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Min-hwa Chi ,  Ajey Jacob ,  Abhijeet Paul

IPC: H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/161 ,  H01L21/02 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/308 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66 ,  H01L29/10

Abstract: A method of forming a multi-valued logic transistor with a small footprint and the resulting device are disclosed. Embodiments include forming plural fins on a silicon substrate, each fin covered with a hardmask; filling spaces between the fins and hard masks with an oxide; removing the hardmasks and recessing each fin, forming a cavity in the oxide over each fin; forming plural Si-based layers in each cavity with an increasing percentage of Ge or C or with an decreasing concentration of dopant from a bottom layer to a top layer; performing CMP for planarization to a top of the fins; recessing the oxide to a depth slightly below a top portion of the fin having a thickness equal to a thickness of each Si-based layer; and forming a high-k gate dielectric and a metal gate electrode over the plural Si-based layers.