公开(公告)号：US4048519A

公开(公告)日：1977-09-13

申请号：US717705

申请日：1976-08-25

申请人： Kurt Hoffmann ,  Guenther Meusburger ,  Gottfried Wotruba

发明人： Kurt Hoffmann ,  Guenther Meusburger ,  Gottfried Wotruba

IPC分类号： G11C27/04 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  H01L29/768 ,  H03H7/30 ,  H03H11/26 ,  H03K5/02 ,  H01L29/78 ,  H03K5/18

CPC分类号： H03K5/023 ,  G11C11/24 ,  G11C11/34 ,  G11C19/28 ,  G11C19/285 ,  H01L29/76825 ,  H03H7/30

摘要： Regenerator circuit for CCD elements in which charge representing information is transferred from a first CCD element to a second CCD element. The circuit includes a first MOS capacitance and a second capacitance connected in series with the first capacitance, the point at which the two capacitances are connected with one another being connected to the input of said second CCD. The output of the first CCD includes an output stage having an output diffusion zone. A transistor is connected between a terminal to which a potential .phi..sub.v can be connected and the point between said first and second capacitances. This transistor has a gate electrode which is connected by a line to the output diffusion zone of the first CCD.

摘要翻译： 用于CCD元件的再生电路，其中表示信息的电荷从第一CCD元件传送到第二CCD元件。 电路包括与第一电容串联连接的第一MOS电容和第二电容，两个电容彼此连接的点被连接到所述第二CCD的输入端。 第一CCD的输出包括具有输出扩散区的输出级。 晶体管连接在可以连接电位ph的端子与所述第一和第二电容之间的点之间。 该晶体管具有通过线连接到第一CCD的输出扩散区的栅电极。

公开(公告)号：US4027294A

公开(公告)日：1977-05-31

申请号：US607196

申请日：1975-08-25

申请人： Guenther Meusburger ,  Gottfried Wotruba

发明人： Guenther Meusburger ,  Gottfried Wotruba

IPC分类号： G11C11/401 ,  G11C11/404 ,  G11C11/4099 ,  G11C7/06

CPC分类号： G11C11/4099 ,  G11C11/404

摘要： A compensation element and method for operating the same, for use with dynamic semiconductor stores, employing a main storage element operatively connected to a word line and a bit line, and an evaluator circuit operatively connected to the bit line, by means of which the storage element may be read out, comprising the steps of capacitively coupling a correcting voltage to the bit line which may be selectively applied thereto in response to signals on a compensation-selector line operative to control the application of said correcting voltage to the bit line whereby the same is raised to the most favorable middle potential of U.sub.BD =0.5 (U.sub.BO + U.sub.Bl), in which U.sub.BO = read outvoltage resulting from storage of a binary "0", and U.sub.Bl = read out voltage resulting from storage of a binary "1".

摘要翻译： 一种用于操作其的补偿元件和方法，用于动态半导体存储器，采用可操作地连接到字线和位线的主存储元件，以及可操作地连接到位线的评估器电路，借助于该存储器 可以读出元件，其包括以下步骤：响应于补偿选择器线路上的信号而将校正电压电容耦合到位线，该位线可被选择性地施加到位线，所述补偿选择器线路上的信号可操作以控制将所述校正电压施加到位线，由此， UBD = U（UBO + UB1）的最有利的中间电位相同，UBO =由存储二进制“0”而产生的读出电压，UB1 =由存储二进制“1”而产生的读出电压 。

公开(公告)号：US4272693A

公开(公告)日：1981-06-09

申请号：US71539

申请日：1979-08-31

申请人： Guenther Meusburger

发明人： Guenther Meusburger

IPC分类号： G11C19/28 ,  G11C27/04 ,  H01L21/339 ,  H01L27/14 ,  H01L29/417 ,  H01L29/762 ,  H01L29/768 ,  H03K3/353

CPC分类号： G11C27/04 ,  G11C19/285 ,  H01L29/76825

摘要： A CCD arrangement which includes a semiconductor layer of a first conductivity type, a layer of insulating material on the semiconductor layer, a row of shift electrodes on the insulating layer. The row of shift electrodes on the insulating layer are fed with pulse train voltages displaced in phase relative to one another. The charges are fed to an output end diffusion zone of the opposite conductivity type which has previously been brought to a reference potential and then released from the latter producing a state which is not bound in potential to the exterior. One of the shift electrodes is connected via a terminal to a transistor switch which intermittently supplies the assigned pulse train voltage, and to the gate of a field effect capacitor whose counter electrode is fed with a periodic pulse voltage. The rising flanks of this pulse voltage are each delayed relative to the times at which the assigned pulse train voltage is interrupted. The terminal of the aforesaid one shift electrode is connected to the gate of a field effect capacitor which serves as a signal output.

摘要翻译： 一种CCD装置，其包括第一导电类型的半导体层，半导体层上的绝缘材料层，绝缘层上的一排移位电极。 绝缘层上的一列移位电极被馈送相对于彼此相位移位的脉冲串电压。 电荷被馈送到相对导电类型的输出端扩散区，其预先已经被引到参考电位，然后从后者释放，产生不与外部结合的状态。 一个移位电极通过端子连接到间歇地提供分配的脉冲序列电压的晶体管开关，以及对向电极馈送周期性脉冲电压的场效应电容器的栅极。 该脉冲电压的上升沿相对于分配的脉冲序列电压被中断的时间延迟。 上述一个移位电极的端子连接到用作信号输出的场效应电容器的栅极。

公开(公告)号：US6120178A

公开(公告)日：2000-09-19

申请号：US434200

申请日：1999-11-04

申请人： Guenther Meusburger ,  Nicolas Jeannet ,  Rudolf Bugmann

发明人： Guenther Meusburger ,  Nicolas Jeannet ,  Rudolf Bugmann

IPC分类号： G04D7/00 ,  G04G3/02 ,  G04B18/00

CPC分类号： G04G3/022

摘要： A method for adjusting the rate of a horological module, said horological module including a printed circuit (1) on which are mounted in particular a quartz (10) and an integrated circuit (20) including an oscillator (21) driven by the quartz (10), a frequency divider circuit (22) with several stages (22.1 to 22.15), an adjustment circuit (23) allowing the introduction of a correction factor of the division ratio of said frequency divider circuit (22), and a memory circuit (24) containing data (N) representing said correction factor. The adjustment method according to the present invention uses a laser device to allow said data (N) representing the correction factor to be coded by the selective destruction of fuses (F1, F2; F.1 to F.6; F.1* to F.6*) forming memory elements of said memory circuit (24).

摘要翻译： 一种用于调节钟表模块的速率的方法，所述钟表模块包括印刷电路（1），特别安装有石英（10）和集成电路（20），所述集成电路包括由石英驱动的振荡器（21） 10），具有多级（22.1至22.15）的分频器电路（22），允许引入所述分频器电路（22）的分频比的校正因子的调节电路（23）和存储器电路 24）包含表示所述校正因子的数据（N）。 根据本发明的调整方法使用激光装置来通过选择性地破坏熔丝（F1，F2; F.1至F.6; F.1 *至...）来代表表示校正因子的所述数据（N） F.6 *）形成所述存储电路（24）的存储元件。

公开(公告)号：US4197554A

公开(公告)日：1980-04-08

申请号：US898489

申请日：1978-04-20

申请人： Guenther Meusburger ,  Karlheinrich Horninger

发明人： Guenther Meusburger ,  Karlheinrich Horninger

IPC分类号： H01L27/10 ,  G11C11/35 ,  G11C11/404 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  H01L27/02

CPC分类号： H01L27/10805 ,  G11C11/35 ,  G11C11/404

摘要： A monolithic integrated circuit arrangement is disclosed which is formed of a group of one-transistor storage elements arranged on a semiconductor layer. Each storage element has a selection field effect transistor and a storage capacitor. The storage elements are arranged in pairs. First and second storage capacitors of each pair are combined to save storage area. In one embodiment, a first conductive coating overlying a surface of the semiconductor layer is employed as a common second electrode for all the storage capacitors. Additional second conductive coatings insulated from the first conductive coating and arranged thereover form the first electrodes for the storage capacitors. In another embodiment a first conductive coating is employed as a common second electrode for the storage capacitors. A second conductive coating is utilized as a first electrode for some of the storage electrodes while an inversion or diffusion layer is utilized as a first electrode for the other storage capacitors. In a final embodiment a first conductive coating over the semiconductor layer is utilized as a common second electrode for all of the storage capacitors. A second conductive coating over the first conductive coating and insulated therefrom is utilized as a first electrode for some of the storage capacitors whereas other storage capacitors have their first electrode formed as an inversion layer adjacent to a shift electrode.

摘要翻译： 公开了一种单片集成电路装置，其由布置在半导体层上的一组单晶体管存储元件形成。 每个存储元件具有选择场效应晶体管和存储电容器。 存储元件成对配置。 每对的第一和第二存储电容器被组合以节省存储区域。 在一个实施例中，覆盖半导体层的表面的第一导电涂层被用作所有存储电容器的公共第二电极。 与第一导电涂层绝缘并且布置在其上的另外的第二导电涂层形成用于存储电容器的第一电极。 在另一个实施例中，第一导电涂层用作存储电容器的公共第二电极。 第二导电涂层用作一些存储电极的第一电极，而反转或扩散层用作其它存储电容器的第一电极。 在最终实施例中，将半导体层上的第一导电涂层用作所有存储电容器的公共第二电极。 第一导电涂层上的第二导电涂层被用作一些存储电容器的第一电极，而其它存储电容器的第一电极形成为与移位电极相邻的反转层。

公开(公告)号：US4035207A

公开(公告)日：1977-07-12

申请号：US712754

申请日：1976-08-09

申请人： Guenther Meusburger ,  Hartmut Runge

发明人： Guenther Meusburger ,  Hartmut Runge

IPC分类号： H01L27/092 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238 ,  H01L27/085 ,  H01L29/78 ,  H01L21/225

CPC分类号： H01L21/8238 ,  H01L21/265 ,  H01L21/2652 ,  H01L21/266 ,  H01L27/085

摘要： A process for producing an integrated circuit having a pair of complementary field effect transistors, one being a J-FET and the other being a MIS-FET. The process includes a series of masking and ion implantation steps carried out in part for both transistors at the same time. The doping of the region between the source and drain is increased for the MIS-FET at the same time that the doping of the channel of the J-FET is increased in order to control the threshold voltage of the MIS-FET.

摘要翻译： 一种用于制造具有一对互补场效应晶体管的集成电路的工艺，一个是J-FET，另一个是MIS-FET。 该方法包括同时对两个晶体管部分执行的一系列掩蔽和离子注入步骤。 为了控制MIS-FET的阈值电压，增加了用于MIS-FET的区域的掺杂，同时增加了J-FET的沟道的掺杂。

公开(公告)号：US4242603A

公开(公告)日：1980-12-30

申请号：US907013

申请日：1978-05-18

申请人： Guenther Meusburger ,  Karl Knauer ,  Jenoe Tihanyi

发明人： Guenther Meusburger ,  Karl Knauer ,  Jenoe Tihanyi

IPC分类号： H01L27/108 ,  G11C11/34 ,  G11C11/35 ,  H01L21/8242 ,  H01L29/10 ,  H01L29/78 ,  H01L27/04

CPC分类号： H01L29/78 ,  G11C11/34 ,  G11C11/35 ,  H01L29/1033

摘要： A dynamic storage element has an electrically insulating layer carried on a substrate of semiconductor material. A conductor path, provided with a terminal, is arranged on the electrically insulating layer, and first and second zones, doped oppositely to the substrate, are provided on the surface of the substrate. The zones are spaced from one another. In that region of the substrate between the zones the substrate is more highly doped with dopants of the same type as those contained in the substrate and the conductor path extends above the highly doped region.

摘要翻译： 动态存储元件具有承载在半导体材料的衬底上的电绝缘层。 设置有端子的导体路径设置在电绝缘层上，并且在衬底的表面上设置与衬底相反掺杂的第一和第二区域。 这些区域彼此间隔开。 在这些区域之间的衬底的该区域中，衬底更加掺杂与衬底中包含的掺杂物相同类型的掺杂剂，并且导体路径在高掺杂区域上方延伸。