公开(公告)号：US5712652A

公开(公告)日：1998-01-27

申请号：US602599

申请日：1996-02-16

申请人： Hajime Sato ,  Shuichiro Ishizawa ,  Nozomu Harada ,  Kiyofumi Ochii ,  Shigeyuki Hayakawa ,  Yoshiro Aoki

发明人： Hajime Sato ,  Shuichiro Ishizawa ,  Nozomu Harada ,  Kiyofumi Ochii ,  Shigeyuki Hayakawa ,  Yoshiro Aoki

IPC分类号： G02F1/1333 ,  G02F1/133 ,  G02F1/136 ,  G02F1/1368 ,  G06F3/033 ,  G09G3/36 ,  H04N5/66

CPC分类号： G09G3/3688 ,  G06F3/03542 ,  G09G3/3648 ,  G09G3/3659 ,  G09G2300/0842 ,  G09G2300/0857 ,  G09G2310/0232 ,  G09G2330/021

摘要： A liquid crystal display device of low power consumption is disclosed, which is suitable for use with a portable data processing apparatus, in particular. The liquid crystal display device, comprises: a switch element array substrate (301) having a plurality of data lines (1) and a plurality of scanning lines (2) both arranged being intersected to each other in a matrix form so as to form matrix intersection points; a plurality of pixel electrodes (3) each arranged for each matrix intersection point; and a plurality of first switching elements (6, 7) each arranged for each matrix intersection point and each turned on or off by the scanning line, for applying write voltage supplied from the data line to the pixel electrode, respectively when turned on; a counter substrate (314) having a plurality of counter electrodes (12) each arranged being opposed to each pixel electrode with a gap between the two; a liquid crystal layer (13) sandwiched between the switching element array substrate and the counter substrate; a plurality of memory elements (100) each interposed between the corresponding first switching element and the corresponding pixel electrode, for holding the write voltage supplied through the data line as data, when the first switching element is turned on; a plurality of display control lines (8, 10) each arranged in correspondence to each scanning line; and a plurality of second switching elements (9, 11) each arranged for each matrix intersection point, for controlling connection between the pixel electrode and the display control line on the basis of output of the memory element.

摘要翻译： 公开了一种低功耗的液晶显示装置，其特别适用于便携式数据处理装置。 液晶显示装置包括：具有多个数据线（1）和多个扫描线（2）的开关元件阵列基板（301），两个扫描线（2）以矩阵形式彼此相交以形成矩阵 交点; 每个矩阵交点设置多个像素电极（3）; 以及多个第一开关元件（6,7），每个第一开关元件分别布置在每个矩阵交点上，并且每个由扫描线导通或截止，用于当打开时分别将从数据线提供的写入电压施加到像素电极; 具有多个对置电极（12）的对置基板（314），每个对置电极（12）与每个像素电极相对设置，在两者之间具有间隙; 夹在开关元件阵列基板和对置基板之间的液晶层（13）; 当所述第一开关元件导通时，分别插入在所述对应的第一开关元件和所述对应的像素电极之间的多个存储元件（100），用于保持通过所述数据线提供的写入电压作为数据; 多个显示控制线（8,10），每个显示控制线对应于每条扫描线布置; 以及多个第二开关元件（9,11），每个第二开关元件（9,11）被布置用于每个矩阵交点，用于基于存储元件的输出来控制像素电极和显示控制线之间的连接。

公开(公告)号：US5276647A

公开(公告)日：1994-01-04

申请号：US813438

申请日：1991-12-26

申请人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Tohru Furuyama ,  Shigeyuki Hayakawa ,  Kiyofumi Ochii

IPC分类号： G11C11/413 ,  G01R31/28 ,  G11C8/12 ,  G11C29/00 ,  G11C29/02 ,  G11C29/06 ,  G11C29/50 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C29/025 ,  G11C29/02 ,  G11C29/50 ,  G11C8/12 ,  G11C11/41

摘要： SRAM comprises a word line driving circuit selecting a predetermined number of word lines in accordance with an input address at the time of a normal operation, and simultaneously selecting all word lines or word lines, which are more than the number of word lines to be selected at the time of the normal operation, at the time of a voltage stress applying test, and a bit line load circuit applying a predetermined bias voltage to said pair of bit lines at the time of the normal operation, and controlling the bias voltage not to be applied to at least one of said pair of bit lines or applying the bias voltage, which is lower than the bias voltage at the time of the normal operation, at the time of the voltage stress test.

摘要翻译： SRAM包括字线驱动电路，其根据正常操作时的输入地址选择预定数量的字线，并且同时选择大于所选择的字线数量的所有字线或字线 在正常工作时，在电压应力测试时，以及在正常工作时向所述一对位线施加预定偏置电压的位线负载电路，并且将偏置电压控制为不 施加到所述一对位线中的至少一个或在电压应力测试时施加低于正常操作时的偏置电压的偏置电压。

公开(公告)号：US5204834A

公开(公告)日：1993-04-20

申请号：US705558

申请日：1991-05-24

申请人： Kiyofumi Ochii ,  Shigeyuki Hayakawa

发明人： Kiyofumi Ochii ,  Shigeyuki Hayakawa

IPC分类号： G11C5/14 ,  G11C11/412 ,  G11C11/413 ,  H01L21/8244 ,  H01L27/11

CPC分类号： G11C5/147 ,  G11C11/412

摘要： A plurality of static memory cells 10 each comprising a thin film transistor acting as a load are connected to a power source wiring 12 positioned within a memory cell array. The power source wiring 12 positioned within the memory cell array is connected via a resistor circuit 14 to a power source wiring 13 of a low resistivity, which is positioned outside the memory cell array.

公开(公告)号：US5281843A

公开(公告)日：1994-01-25

申请号：US717805

申请日：1991-06-19

申请人： Kiyofumi Ochii ,  Shigeyuki Hayakawa

发明人： Kiyofumi Ochii ,  Shigeyuki Hayakawa

IPC分类号： G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  G11C11/34 ,  H01L29/40

CPC分类号： H01L29/78648 ,  G11C11/412 ,  H01L27/1108 ,  H01L29/78645 ,  Y10S257/903 ,  Y10S257/904

摘要： First and second N-channel MOS transistors, each serving as a transfer gate, have their current paths connected, at their first ends, to bit lines, respectively, and their gates connected to a word line. Third and fourth N-channel MOS transistors, forming a flip-flop circuit, have their current paths connected, at their first ends, to the second ends of the current paths of the first and second transistors, respectively, and at their second ends, to a first power supply. The first ends of the current paths of the third and fourth transistors are connected to first ends of first and second thin-film transistors, respectively. The second ends of the current paths of the first and second thin-film transistors are connected to a second power supply. Each of the first and second thin-film transistors has first and second gates on both sides of its channel region. The first and second gates of the first thin-film transistor are connected to the gate of the fourth transistor, while the first and second gates of the second thin-film transistor are connected to the gate of the third transistor. Thus, the first and second thin-film transistors are supplied with a potential to render them nonconductive.

摘要翻译： 每个用作传输门的第一和第二N沟道MOS晶体管的电流路径分别在它们的第一端连接到位线，并且它们的栅极连接到字线。 形成触发电路的第三和第四N沟道MOS晶体管的电流路径在其第一端分别连接到第一和第二晶体管的电流路径的第二端，并且在其第二端， 到第一个电源。 第三和第四晶体管的电流路径的第一端分别连接到第一和第二薄膜晶体管的第一端。 第一和第二薄膜晶体管的电流路径的第二端连接到第二电源。 第一和第二薄膜晶体管中的每一个在其沟道区域的两侧具有第一和第二栅极。 第一薄膜晶体管的第一和第二栅极连接到第四晶体管的栅极，而第二薄膜晶体管的第一和第二栅极连接到第三晶体管的栅极。 因此，第一和第二薄膜晶体管被提供有使其不导电的电位。

公开(公告)号：US5563434A

公开(公告)日：1996-10-08

申请号：US468385

申请日：1995-06-06

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： G11C11/404 ,  G11C11/4074 ,  H01L27/108 ,  H01L29/92 ,  G11C11/401 ,  G11C11/409

CPC分类号： G11C11/404 ,  G11C11/4074 ,  H01L27/108

摘要： The gate of a selection transistor is connected to a word line and the source thereof is connected to a bit line. The drain of the selection transistor is connected to a storage node constituting a capacitor of thin film transistor structure. The capacitor has a plate electrode insulated from the storage node, that portion of the plate electrode which is disposed in opposition to the storage node is formed to have an impurity concentration lower than the remaining portion thereof and an inverted layer is formed in the corresponding portion according to data stored in the storage node. The plate electrode is connected to pulse generation means, a pulse signal is output from the pulse generation means in the data readout operation and the potential of the plate electrode is raised by the pulse signal.

摘要翻译： 选择晶体管的栅极连接到字线，其源极连接到位线。 选择晶体管的漏极连接到构成薄膜晶体管结构的电容器的存储节点。 电容器具有与存储节点绝缘的平板电极，与存储节点相对设置的板电极的部分形成为具有低于其余部分的杂质浓度，并且反相层形成在相应部分中 根据存储在存储节点中的数据。 平板电极连接到脉冲产生装置，在数据读出操作中从脉冲发生装置输出脉冲信号，并且通过脉冲信号使平板电极的电位升高。

公开(公告)号：US5282162A

公开(公告)日：1994-01-25

申请号：US704923

申请日：1991-05-23

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： G11C11/405 ,  H01L27/108 ,  G11C11/40

CPC分类号： H01L27/108 ,  G11C11/405

摘要： The gate of a transistor Q1 serving as a selection transistor is connected to a word line and the source thereof is connected to a bit line BL. The gate of a transistor Q2 serving as a cell capacitor is connected to the drain of the transistor Q1 and the drain thereof is connected to a pulse generation circuit. Whether an inverted layer is formed in the channel region of the transistor Q2 or not is determined according to the stored data. An inverted layer is formed in the channel region of the transistor Q2 having data "1" stored as storage data. The source of the transistor Q2 is connected to the gate of a transistor Q3. The drain of the transistor Q3 is connected to a pulse generation circuit 11 and the source thereof is connected to the drain of the transistor Q1. The transistor Q2 having an inverted layer formed therein is turned on when a preset voltage is supplied from the pulse generation circuit 11 in the stored data reading operation, and in this case, the transistor Q3 is turned on. Therefore, a current can be supplied to the bit line BL from the pulse generation circuit 11 via the transistor Q3 and the selected transistor Q1.

摘要翻译： 用作选择晶体管的晶体管Q1的栅极连接到字线，其源极连接到位线BL。 用作单元电容器的晶体管Q2的栅极连接到晶体管Q1的漏极，其漏极连接到脉冲发生电路。 根据存储的数据确定在晶体管Q2的沟道区域中是否形成反相层。 在具有作为存储数据存储的数据“1”的晶体管Q2的沟道区域中形成反相层。 晶体管Q2的源极连接到晶体管Q3的栅极。 晶体管Q3的漏极连接到脉冲发生电路11，其源极连接到晶体管Q1的漏极。 当在存储的数据读取操作中从脉冲发生电路11提供预置电压时，形成有反相层的晶体管Q2导通，在这种情况下，晶体管Q3导通。 因此，可以经由晶体管Q3和所选择的晶体管Q1从脉冲发生电路11向位线BL提供电流。

公开(公告)号：US5132929A

公开(公告)日：1992-07-21

申请号：US288183

申请日：1988-12-22

申请人： Kiyofumi Ochii

发明人： Kiyofumi Ochii

IPC分类号： H01L27/10 ,  G11C11/412 ,  G11C11/413 ,  G11C11/419 ,  G11C29/00 ,  G11C29/04 ,  G11C29/50 ,  H01L21/66

CPC分类号： G11C11/412 ,  G11C11/419 ,  G11C29/50 ,  G11C11/41 ,  G11C2029/5006 ,  H01L2924/0002

摘要： A static random access memory has a plurality of memory cells. Each memory cell is made up of two high-resistance resistors functioning as load elements, and a flip-flop circuit. The flip-flop circuit is made up of two inverters including MOS transistors which are formed in a substrate and used as drive elements. The sources of the two MOS transistors are coupled to each other and electrically isolated from the substrate. Another MOS transistor is connected between the common source of the flip-flop MOS transistors and the source of a power-supply voltage. A MOS transistor is coupled between the common source of the MOS transistors and the source of a ground voltage. A plurality of bit lines supplies data to, and receives data from, the memory cells. A resistance element is connected between each bit line and the source of the power-supply voltage, and an output terminal outputs the voltage at one end of this resistance element. Two different voltages are applied to the sources of the two MOS transistors. One voltage is applied during normal operation of the memory and the other voltage is applied during leakage current detection testing.

摘要翻译： 静态随机存取存储器具有多个存储单元。 每个存储单元由用作负载元件的两个高电阻电阻器和触发器电路组成。 触发器电路由两个反相器组成，包括形成在衬底中并用作驱动元件的MOS晶体管。 两个MOS晶体管的源极彼此耦合并与衬底电隔离。 另一MOS晶体管连接在触发器MOS晶体管的公共源和电源电压源之间。 MOS晶体管耦合在MOS晶体管的公共源和接地电压源之间。 多个位线向存储器单元提供数据并从存储单元接收数据。 电阻元件连接在每个位线和电源电压源之间，输出端输出该电阻元件一端的电压。 两个不同的电压施加到两个MOS晶体管的源极。 在存储器的正常运行期间施加一个电压，并且在泄漏电流检测测试期间施加另一个电压。

公开(公告)号：US4710897A

公开(公告)日：1987-12-01

申请号：US726698

申请日：1985-04-24

申请人： Fujio Masuoka ,  Kiyofumi Ochii

发明人： Fujio Masuoka ,  Kiyofumi Ochii

IPC分类号： H01L29/94 ,  H01L23/532 ,  H01L27/11 ,  H01L27/10 ,  G11C11/40 ,  H01L23/50 ,  H01L29/04

CPC分类号： H01L27/1104 ,  H01L23/53271 ,  H01L2924/0002 ,  Y10S257/903

摘要： The gate electrode of a first CMOS inverter is connected to the drains of each transistor of a second CMOS inverter via an interconnection, and the gate electrode of the second CMOS inverter is connected to the drains of the first CMOS inverter via an interconnection, to form a flip-flop circuit. A pair of transfer transistors are connected to the nodes of this flip-flop circuit. A plurality of memory cells each constructed by the flip-flop circuit and the pair of transfer transistors are integrated in a matrix form to form a semiconductor memory device. The pair of gate electrodes are formed of a first polycrystalline silicon layer which includes an impurity of the first conductivity type. The pair of interconnections are formed of an impurity-doped second polycrystalline silicon layer and a high-melting point metal layer, and formed on a first interlayer insulation film. The high-melting point metal layer is provided to prevent an increase in the resistance value due to the formation of a pn junction formed by the interconnections.

摘要翻译： 第一CMOS反相器的栅电极通过互连连接到第二CMOS反相器的每个晶体管的漏极，并且第二CMOS反相器的栅电极经由互连连接到第一CMOS反相器的漏极，以形成 触发电路。 一对传输晶体管连接到该触发器电路的节点。 由触发器电路和一对转移晶体管构成的多个存储单元以矩阵形式集成以形成半导体存储器件。 一对栅电极由包括第一导电类型的杂质的第一多晶硅层形成。 一对互连由杂质掺杂的第二多晶硅层和高熔点金属层形成，并形成在第一层间绝缘膜上。 提供高熔点金属层以防止由互连形成的pn结的形成导致的电阻值的增加。

公开(公告)号：US4136292A

公开(公告)日：1979-01-23

申请号：US827721

申请日：1977-08-25

申请人： Yasoji Suzuki ,  Kiyofumi Ochii

发明人： Yasoji Suzuki ,  Kiyofumi Ochii

IPC分类号： G11C11/409 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/412 ,  G11C11/419 ,  H03K5/02 ,  H03K5/20

CPC分类号： G11C11/419 ,  G11C11/4091 ,  H03K5/023

摘要： A voltage sensing circuit of differential input type includes at least one differential amplifier circuit connected between two complementary data lines of a semiconductor memory. The differential amplifier circuit detects data in response to a minute potential difference between the data lines and amplifies the same by a substantial change in conductance g.sub.m of metal oxide semiconductor field effect transistors (MOSFET) used in the circuit. When data is read from a semiconductor memory onto the data lines, the differential amplifier sensing circuit detects the data quickly by detecting potential changes of the data lines.

公开(公告)号：US5239501A

公开(公告)日：1993-08-24

申请号：US735047

申请日：1991-07-24

申请人： Masataka Matsui ,  Kiyofumi Ochii

发明人： Masataka Matsui ,  Kiyofumi Ochii

IPC分类号： G11C11/41

CPC分类号： G11C11/41

摘要： In a static memory, a memory cell is constituted by only the same-channel MOSFETs. With the MOSFETs of the same channel, no well isolation region is required, and a cell size can be decreased. Moreover, the high potential side power source of a flip-flop can be used as a read word line. Thus the read word line can be driven by an ECL logic circuit.

摘要翻译： 在静态存储器中，存储单元仅由相同通道的MOSFET构成。 使用相同通道的MOSFET，不需要良好的隔离区域，并且可以减小单元尺寸。 此外，触发器的高电位侧电源可以用作读字线。 因此，读取字线可以由ECL逻辑电路驱动。