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公开(公告)号：US20080246031A1
公开(公告)日：2008-10-09
申请号：US11784632
申请日：2007-04-09
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Hsien-Wei Chen , Benson Liu , Chia-Lun Tsai , Anbiarshy N.F. Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Hsien-Wei Chen , Benson Liu , Chia-Lun Tsai , Anbiarshy N.F. Wu
IPC分类号： H01L23/544 , H01L21/66
CPC分类号： H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor structure is provided. The semiconductor structure includes a semiconductor chip and a scribe line adjoining the semiconductor chip. A conductive feature is formed in the scribe line and exposed on the surface of the scribe lines, wherein the conductive feature has an edge facing the semiconductor chip. A kerf path is in the scribe line. A first cut is formed in the conductive feature, wherein the first cut extends from the first edge to the kerf path.
摘要翻译： 提供半导体结构。 半导体结构包括半导体芯片和与半导体芯片相邻的划线。 导电特征形成在划线中并暴露在划线的表面上，其中导电特征具有面向半导体芯片的边缘。 切割路径在划线中。 在导电特征中形成第一切口，其中第一切口从第一边缘延伸到切口路径。
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公开(公告)号：US20090091032A1
公开(公告)日：2009-04-09
申请号：US11868850
申请日：2007-10-08
申请人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N.F. Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N.F. Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/05552 , H01L2224/05599 , H01L2224/0603 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082
摘要： A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
摘要翻译： 公开了一种焊盘设计，其包括半导体器件上的一个或多个焊盘组。 每个焊盘组由具有交替取向的两个或更多个焊盘组成，使得相邻的焊盘相对于相邻的焊盘在相对的两侧具有焊接球。
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公开(公告)号：US20080191205A1
公开(公告)日：2008-08-14
申请号：US11706940
申请日：2007-02-13
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
IPC分类号： H01L23/58
CPC分类号： H01L23/585 , H01L22/34 , H01L24/11 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/45147 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
摘要翻译： 半导体结构包括与半导体芯片的边缘相邻的菊花链。 菊花链包括分布在多个金属化层中的多个水平金属线，其中水平金属线串联连接; 在相同层中的多个连接焊盘并且电连接水平金属线，其中连接焊盘在物理上彼此分离; 以及多个垂直金属线，每个将所述连接焊盘中的一个连接到所述水平金属线之一，其中所述多个连接焊盘中的一个连接焊盘中的一个连接焊盘仅通过所述多个垂直金属线中的一个垂直连接 金属线 以及与菊花链相邻且电气断开的密封环。
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公开(公告)号：US08227917B2
公开(公告)日：2012-07-24
申请号：US11868850
申请日：2007-10-08
申请人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N. F. Wu , Shang-Yun Hou , Shin-Puu Jeng
发明人： Shih-Hsun Hsu , Hao-Yi Tsai , Benson Liu , Chia-Lun Tsai , Hsien-Wei Chen , Anbiarshy N. F. Wu , Shang-Yun Hou , Shin-Puu Jeng
IPC分类号： H01L23/48
CPC分类号： H01L24/06 , H01L22/32 , H01L24/05 , H01L2224/05552 , H01L2224/05599 , H01L2224/0603 , H01L2924/00014 , H01L2924/01005 , H01L2924/01006 , H01L2924/01015 , H01L2924/01033 , H01L2924/01076 , H01L2924/01082
摘要： A bonding pad design is disclosed that includes one or more pad groups on a semiconductor device. Each pad group is made up of two or more bonding pads that have an alternating orientation, such that adjacent bonding pads have their bond ball on opposite sides in relation to the adjacent bonding pad.
摘要翻译： 公开了一种焊盘设计，其包括半导体器件上的一个或多个焊盘组。 每个焊盘组由具有交替取向的两个或更多个焊盘组成，使得相邻的焊盘相对于相邻的焊盘在相对的两侧具有焊接球。
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公开(公告)号：US09601443B2
公开(公告)日：2017-03-21
申请号：US11706940
申请日：2007-02-13
申请人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
发明人： Hao-Yi Tsai , Shih-Hsun Hsu , Shih-Cheng Chang , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai , Benson Liu , Shin-Puu Jeng , Anbiarshy Wu
CPC分类号： H01L23/585 , H01L22/34 , H01L24/11 , H01L2224/0554 , H01L2224/05548 , H01L2224/05573 , H01L2224/05624 , H01L2224/05639 , H01L2224/05647 , H01L2224/05684 , H01L2224/45147 , H01L2224/48091 , H01L2924/00014 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor structure includes a daisy chain adjacent to an edge of a semiconductor chip. The daisy chain includes a plurality of horizontal metal lines distributed in a plurality of metallization layers, wherein the horizontal metal lines are serially connected; a plurality of connecting pads in a same layer and electrically connecting the horizontal metal lines, wherein the connecting pads are physically separated from each other; and a plurality of vertical metal lines, each connecting one of the connecting pads to one of the horizontal metal lines, wherein one of the plurality of connecting pads is connected to one of the plurality of horizontal metal lines by only one of the plurality of vertical metal lines; and a seal ring adjacent and electrically disconnected from the daisy chain.
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公开(公告)号：US08519512B2
公开(公告)日：2013-08-27
申请号：US11525575
申请日：2006-09-22
申请人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
发明人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L21/782 , H01L21/784 , H01L21/786 , H01L22/10 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.
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公开(公告)号：US20080073753A1
公开(公告)日：2008-03-27
申请号：US11525575
申请日：2006-09-22
申请人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
发明人： Hao-Yi Tsai , Chia-Lun Tsai , Shang-Yun Hou , Shin-Puu Jeng , Shih-Hsun Hsu , Wei-Ti Hsu , Lin-Ko Feng , Chun-Jen Chen
IPC分类号： H01L23/544
CPC分类号： H01L21/78 , H01L21/782 , H01L21/784 , H01L21/786 , H01L22/10 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor wafer structure includes a plurality of dies, a first scribe line extending along a first direction, a second scribe line extending along a second direction and intersecting the first scribe line, wherein the first and the second scribe lines have an intersection region. A test line is formed in the scribe line, wherein the test line crosses the intersection region. Test pads are formed in the test line and only outside a free region defined substantially in the intersection region.
摘要翻译： 半导体晶片结构包括多个模具，沿着第一方向延伸的第一划线，沿着第二方向延伸并且与第一划线交叉的第二划线，其中第一划线和第二划线具有交叉区域。 在划线中形成测试线，其中测试线穿过交叉区域。 测试垫形成在测试线中，并且仅在基本上在交叉区域中限定的自由区域的外部。
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公开(公告)号：US07449785B2
公开(公告)日：2008-11-11
申请号：US11347378
申请日：2006-02-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05082 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.
摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。
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公开(公告)号：US20070182007A1
公开(公告)日：2007-08-09
申请号：US11347378
申请日：2006-02-06
申请人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
发明人： Shin-Puu Jeng , Hao-Yi Tsai , Shang-Yun Hou , Hsien-Wei Chen , Chia-Lun Tsai
CPC分类号： H01L24/12 , H01L23/3192 , H01L24/03 , H01L24/05 , H01L24/11 , H01L2224/0401 , H01L2224/05082 , H01L2224/05558 , H01L2224/05572 , H01L2224/05624 , H01L2224/05647 , H01L2224/13022 , H01L2224/13099 , H01L2224/131 , H01L2924/0002 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01019 , H01L2924/01022 , H01L2924/01027 , H01L2924/01028 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/0105 , H01L2924/014 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2224/05552
摘要： A solder bump on a semiconductor substrate is provided. The solder bump comprises a semiconductor substrate having a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further comprises a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.
摘要翻译： 提供半导体衬底上的焊料凸块。 焊料凸块包括其上具有顶部铜焊盘的半导体衬底，半导体衬底上的保护层和覆盖保护层的至少一个无机钝化层，第一开口露出顶部铜焊盘，其中无机钝化层具有较薄的 邻近第一开口的顶部的部分。 所述焊料凸块还包括在所述无机钝化层上的软钝化层，其具有大于所述第一开口的第二开口，沿所述第一开口和所述第二开口共形形成的凸块下金属层和形成在所述下凸块金属层上的焊料凸块 。
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公开(公告)号：US20070224794A1
公开(公告)日：2007-09-27
申请号：US11390951
申请日：2006-03-27
申请人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
发明人： Hao-Yi Tsai , Shang-Yun Hou , Anbiarshy Wu , Chia-Lun Tsai , Shin-Puu Jeng
IPC分类号： H01L21/44
CPC分类号： H01L23/5258 , H01L24/11 , H01L2224/13099 , H01L2924/01006 , H01L2924/01013 , H01L2924/01019 , H01L2924/01022 , H01L2924/01025 , H01L2924/01029 , H01L2924/01033 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/04941 , H01L2924/04953 , H01L2924/14
摘要： An integrated circuit structure comprising a fuse and a method for forming the same are provided. The integrated circuit structure includes a substrate, an interconnection structure over the substrate, a fuse connected to the interconnection structure, and an anti-reflective coating (ARC) on the fuse. The ARC has an increased thickness and acts as a remaining oxide, and no further remaining passivation layer exists on the ARC.
摘要翻译： 提供一种包括熔丝的集成电路结构及其形成方法。 集成电路结构包括衬底，衬底上的互连结构，连接到互连结构的熔丝以及熔丝上的抗反射涂层（ARC）。 ARC具有增加的厚度并用作剩余氧化物，并且ARC上不存在进一步的剩余钝化层。
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