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    Source drain and extension dopant concentration
    1.
    发明申请
    Source drain and extension dopant concentration 审中-公开
    源极漏极和延伸掺杂剂浓度

    公开(公告)号：US20050189660A1

    公开(公告)日：2005-09-01

    申请号：US10858644

    申请日：2004-06-02

    申请人： Haowen Bu ,  Amitabh Jain ,  Wayne Bather ,  Stephanie Butler

    发明人： Haowen Bu ,  Amitabh Jain ,  Wayne Bather ,  Stephanie Butler

    IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/76 ,  H01L21/338

    CPC分类号： H01L29/6659 ,  H01L29/6656 ,  H01L29/7833

    摘要： A method of forming a semiconductor device includes forming one or more sidewall spacer layers on the outer surface of a gate stack. At least one region of an at least partially formed semiconductor device is doped. First and second sidewall bodies are formed on opposing sides of the gate stack. The formation of the first and second sidewall bodies includes forming a first sidewall-forming layer on the outward surface of the gate stack and the sidewall spacer layers, exposing the semiconductor device to a heating cycle in a single wafer reactor, and forming a second sidewall-forming layer on the outward surface of the first sidewall-forming layer. The formation of the second sidewall-forming layer occurs in an environment that substantially minimizes dopant loss and deactivation in the at least one region of the partially formed semiconductor device.

    摘要翻译： 形成半导体器件的方法包括在栅叠层的外表面上形成一个或多个侧壁间隔层。 至少部分形成的半导体器件的至少一个区域被掺杂。 第一和第二侧壁体形成在栅极堆叠的相对侧上。 第一和第二侧壁体的形成包括在栅极堆叠的外表面和侧壁间隔层上形成第一侧壁形成层，将半导体器件暴露于单个晶片反应器中的加热循环，以及形成第二侧壁 在第一侧壁形成层的外表面上形成层。 第二侧壁形成层的形成发生在基本上最小化部分形成的半导体器件的至少一个区域中的掺杂剂损失和失活的环境中。

    Antimony ion implantation for semiconductor components
    2.
    发明申请
    Antimony ion implantation for semiconductor components 有权
    半导体元件的锑离子注入

    公开(公告)号：US20070218662A1

    公开(公告)日：2007-09-20

    申请号：US11725927

    申请日：2007-03-20

    申请人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    发明人： Haowen Bu ,  Amitabh Jain ,  Srinivasan Chakravarthi ,  Shashank Ekbote

    IPC分类号： H01L21/425

    CPC分类号： H01L29/6659 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/324 ,  H01L29/6653 ,  H01L29/7833

    摘要： A method is disclosed for implanting and activating antimony as a dopant in a semiconductor substrate. A method is also disclosed for implanting and activating antimony to form a source/drain extension region in the formation of a transistor, in such a manner as to achieve high activation and avoid deactivation via subsequent exposure to high temperatures. This technique facilitates the formation of very thin source/drain regions that exhibit reduced sheet resistance while also suppressing short channel effects. Enhancements to these techniques are also suggested for more precise implantation of antimony to create a shallower source/drain extension, and to ensure formation of the source/drain extension region to underlap the gate. Also disclosed are transistors and other semiconductor components that include doped regions comprising activated antimony, such as those formed according to the disclosed methods.

    摘要翻译： 公开了一种用于在半导体衬底中注入和活化锑作为掺杂剂的方法。 还公开了一种用于注入和活化锑以形成晶体管的源极/漏极延伸区域的方法，以便实现高激活并避免随后暴露于高温而失活。 该技术有助于形成非常薄的源极/漏极区域，其表现出降低的薄层电阻，同时还抑制短沟道效应。 还建议对这些技术的增强用于更精确地注入锑以产生较浅的源极/漏极延伸，并且确保形成源极/漏极延伸区域以使栅极下沉。 还公开了晶体管和其它半导体组件，其包括包含活性锑的掺杂区域，例如根据所公开的方法形成的那些。

    Transistor with improved source/drain extension dopant concentration
    5.
    发明授权
    Transistor with improved source/drain extension dopant concentration 有权
    具有改善的源极/漏极延伸掺杂剂浓度的晶体管

    公开(公告)号：US06743705B2

    公开(公告)日：2004-06-01

    申请号：US10287979

    申请日：2002-11-05

    申请人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

    发明人： Manoj Mehrotra ,  Haowen Bu ,  Amitabh Jain

    IPC分类号： H01L214763

    CPC分类号： H01L29/6659 ,  H01L29/6656

    摘要： A method (40) of forming an integrated circuit (60) device including a substrate (64). The method including the step of first (42), forming a gate stack (62) in a fixed relationship to the substrate, the gate stack including a gate having sidewalls. The method further includes the step of second (42), implanting source/drain extensions (701, 702) into the substrate and self-aligned relative to the gate stack. The method further includes the steps of third (46, 48), forming a first sidewall-forming layer (72) in a fixed relationship to the sidewalls and forming a second sidewall-forming layer (74) in a fixed relationship to the sidewalls. The step of forming a second sidewall-forming layer includes depositing the second sidewall-forming layer at a temperature equal to or greater than approximately 850° C. The method further includes the step of fourth (50), implanting deep source/drain regions (761, 762) into the substrate and self-aligned relative to the gate stack and the first and second sidewall-forming layers.

    摘要翻译： 一种形成包括衬底（64）的集成电路（60）装置的方法（40）。 该方法包括第一步骤（42）的步骤，与衬底形成固定关系的栅叠层（62），栅叠层包括具有侧壁的栅极。 该方法还包括第二步骤（42），将源极/漏极延伸部分（701,702）注入到衬底中并相对于栅极堆叠自对准。 该方法还包括第三（46,48）的步骤，形成与侧壁成固定关系的第一侧壁形成层（72），并形成与侧壁成固定关系的第二侧壁形成层（74）。 形成第二侧壁形成层的步骤包括在等于或大于约850℃的温度下沉积第二侧壁形成层。该方法还包括第四（50）的步骤，将深源/漏区（ 761,762）插入衬底并且相对于栅极堆叠以及第一和第二侧壁形成层自对准。