公开(公告)号：US3950936A

公开(公告)日：1976-04-20

申请号：US522947

申请日：1974-11-11

申请人： Henri J. Oguey ,  Eric Andre Vittoz

发明人： Henri J. Oguey ,  Eric Andre Vittoz

IPC分类号： G04G9/00 ,  G04G9/08 ,  G04G9/12 ,  G09G3/16 ,  G04C3/00

CPC分类号： H03K21/18 ,  G04G9/0047 ,  G04G9/12 ,  G04G9/126 ,  G09G3/16

摘要： A device for providing an electro-optical display of time comprises an electronic timekeeper fed by a voltage source and including a time base and a frequency divider. An electro-optical display is formed of groups of electro-chromic cells each able to take two different visual aspects. The cells are controlled by a code converter supplying state variables corresponding to the desired aspects of the cells to provide a display of time. One aspect of the cells corresponds to a stable state, the other aspect to a quasi-stable state which in order to be maintained, requires very low or zero power. Transition of a cell from one state to another requires precisely determined amounts of energy. A change detector supplies to a selector, data to actuate the operations of inscription and erasure of the display cells. The selector dispenses the required amounts of energy supplied to the display to ensure correspondence between the state variables delivered by the code converter and the aspect of the corresponding display cells, in a manner ensuring transition from one state to another with a minimum supply of energy.

摘要翻译： 用于提供时间的电光显示的装置包括由电压源馈送并包括时基和分频器的电子计时器。 电光显示器由能够采取两个不同视觉方面的电 - 铬电池组形成。 单元由代码转换器控制，该代码转换器提供对应于单元格的期望方面的状态变量以提供时间的显示。 电池的一个方面对应于稳定状态，另一方面为了保持稳定的准稳态，需要非常低或零功率。 细胞从一个状态向另一个状态的转变需要精确确定的能量量。 变更检测器向选择器提供数据，以驱动显示单元的铭刻和擦除操作。 选择器分配提供给显示器的所需能量，以确保代码转换器提供的状态变量与相应显示单元的方面之间的对应关系，以确保以最小的能量供应从一个状态向另一个状态转变。

公开(公告)号：US4041522A

公开(公告)日：1977-08-09

申请号：US605845

申请日：1975-08-19

申请人： Henri J. Oguey ,  Bernard Gerber

发明人： Henri J. Oguey ,  Bernard Gerber

IPC分类号： H01L21/822 ,  H01L21/00 ,  H01L21/8236 ,  H01L21/8238 ,  H01L27/00 ,  H01L27/04 ,  H01L27/06 ,  H01L27/088 ,  H01L27/092 ,  H01L29/78 ,  H03F3/30 ,  H03K3/354 ,  H03K19/0948 ,  H01L27/02 ,  H01L29/04

CPC分类号： H03K19/0948 ,  H01L21/00 ,  H01L27/00 ,  H01L27/0688 ,  H01L27/092 ,  H03F3/3001 ,  H03K3/3545

摘要： An integrated circuit comprises complementary FET having channels extending on the surface of a substrate and on the surface of a well in the substrate and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well. A floating diode, i.e. connected neither to the substrate, nor to a well, is formed simultaneously with the FET by depositing and selectively etching a first doped oxide to cover a first region of the polycrystalline silicon, depositing an oppositely doped oxide over the remainder using the first oxide as mask, and oppositely doping the two regions of polycrystalline silicon by heat treatment. Alternatively, the second region can be doped by treatment in a gaseous phase or by ionic implantation, in either case using the first oxide as mask. Said regions are contiguous under the edge of the first doped oxide to form an autoaligned junction forming said floating diode which has a reverse conductivity notably greater than that of a junction in monocrystalline silicon, and easily reproduceable characteristics.

摘要翻译： 集成电路包括互补FET，其具有在衬底的表面上延伸的沟道和衬底中的阱的表面，以及形成在与衬底和每个所述阱绝缘的多晶硅层中的栅极。 通过沉积和选择性蚀刻第一掺杂氧化物以覆盖多晶硅的第一区域，在FET上同时形成浮动二极管，即既不连接到衬底也不连接到阱，并且通过使用 第一氧化物作为掩模，并且通过热处理相反地掺杂多晶硅的两个区域。 或者，可以通过在气相中或通过离子注入的处理来掺杂第二区域，在使用第一氧化物作为掩模的情况下。 所述区域在第一掺杂氧化物的边缘下连续以形成形成所述浮动二极管的自对准结，其具有显着大于单晶硅中的结的反向导电性和易于再现的特性。

公开(公告)号：US4140924A

公开(公告)日：1979-02-20

申请号：US748287

申请日：1976-12-07

申请人： Henri J. Oguey ,  Eric A. Vittoz

发明人： Henri J. Oguey ,  Eric A. Vittoz

IPC分类号： H03K19/00 ,  G11C19/28 ,  H03K3/356 ,  H03K19/0948 ,  H03K23/54 ,  H03M7/00 ,  H03K21/10 ,  H03K3/286 ,  H03K19/08 ,  H03K23/24

CPC分类号： G11C19/28 ,  H03K19/0948 ,  H03K23/54 ,  H03K3/356104 ,  H03M7/001

摘要： The invention relates to logic CMOS transistor circuits formed by at least one gate circuit, each gate circuit comprising a pair of CMOS transistor groups connected in series between the terminals of a power supply. The conductive state of both groups of transistors defines the potential of a common connection point or output node. A power dissipating means of relatively high resistance is coupled in parallel with at least a part of at least one of the said transistor groups, at least during a time interval in which both groups are in a non conductive state. This results in a quasi static behavior of the circuits according to the invention although the basic structure of the same is that of dynamic circuits.

摘要翻译： 本发明涉及由至少一个门电路形成的逻辑CMOS晶体管电路，每个门电路包括串联在电源端子之间的一对CMOS晶体管组。 两组晶体管的导通状态定义了公共连接点或输出节点的电位。 至少在两组处于非导通状态的时间间隔内，具有相对较高电阻的功率耗散装置与至少一个所述晶体管组的至少一部分并联耦合。 这导致根据本发明的电路的准静态特性，尽管其基本结构是动态电路的基本结构。

公开(公告)号：US5239500A

公开(公告)日：1993-08-24

申请号：US972093

申请日：1992-11-05

申请人： Henri J. Oguey

发明人： Henri J. Oguey

IPC分类号： G11C16/10 ,  G11C27/00

CPC分类号： G11C16/10 ,  G11C27/005

摘要： The process according to the invention is applicable to a non-volatile memory cell with an MOS transistor structure with an insulated floating gate, a control electrode coupled capacitively to the floating gate and an injection zone separated from the floating gate by an injection oxide and capable of injecting or extracting charges into or from the floating gate. The process is characterized in that the control electrode is subjected to an alternating voltage of decreasing amplitude and the injection zone is subjected to a voltage representing the quantity to be stored. The invention applies to the storage of analog quantities.

摘要翻译： 根据本发明的方法可应用于具有MOS晶体管结构的非易失性存储单元，其具有绝缘浮置栅极，电容耦合到浮置栅极的控制电极和通过注入氧化物与浮置栅极分离的注入区域，并且能够 将电荷注入或抽出浮动门。 该方法的特征在于，控制电极经受幅度减小的交流电压，并且注入区域经受表示要存储的量的电压。 本发明适用于存储模拟量。

公开(公告)号：US4628274A

公开(公告)日：1986-12-09

申请号：US728883

申请日：1985-04-30

申请人： Eric A. Vittoz ,  Henri J. Oguey

发明人： Eric A. Vittoz ,  Henri J. Oguey

IPC分类号： H03F3/34 ,  H03F1/30 ,  H03F3/45 ,  H03F1/14

CPC分类号： H03F3/45753 ,  H03F1/303 ,  H03F3/45977

摘要： The invention concerns an amplifier comprising means for compensating for the input drift voltage. During a preparation phase, the input signal of the amplifier (10) is nullified by short-circuiting the inputs (12) and (13) by means of the change-over switch (30) and the output (15) is connected to a capacitor (40) and to a secondary input (14) of the amplifier. The secondary input has a substantially lower gain than the gain relative to the main input (13), which makes it possible substantially to reduce the effect of charge injection caused by opening of the switch (60). In the amplification phase, the input (13) receives an input signal (V1) and the input drift voltage (.alpha.V) is compensated by means of the value stored in the capacitor (40).

摘要翻译： 本发明涉及一种放大器，包括用于补偿输入漂移电压的装置。 在准备阶段期间，放大器（10）的输入信号通过使转换开关（30）短路输入（12）和（13）而无效，并且输出端（15）连接到 电容器（40）和放大器的辅助输入端（14）。 辅助输入具有比相对于主输入（13）的增益明显更低的增益，这使得可能基本上减少由开关（60）的打开引起的电荷注入的影响。 在放大阶段，输入端（13）接收输入信号（V1），通过存储在电容器（40）中的值补偿输入漂移电压（αV）。

公开(公告)号：US4205342A

公开(公告)日：1980-05-27

申请号：US898681

申请日：1978-04-21

申请人： Mougahed Y. Darwish ,  Henri J. Oguey

发明人： Mougahed Y. Darwish ,  Henri J. Oguey

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/78 ,  H01L29/8605 ,  H01L21/22 ,  H01L27/04

CPC分类号： H01L29/7838 ,  H01L27/092 ,  H01L29/8605

摘要： A CMOS integrated circuit structure is provided having circuit elements which can function as high resistances or stable current sources. The circuit elements include a region of intermediate doping which has a surface concentration between that of a substrate and a homogeneous region of a doped pocket formed therein. The region of intermediate doping is formed by the vicinity of two pocket edges, these edges being separated by a distance which is substantially not greater than twice the length of the lateral diffusion of the doping of the pockets.

摘要翻译： 提供了具有可以用作高电阻或稳定电流源的电路元件的CMOS集成电路结构。 电路元件包括中间掺杂的区域，其表面浓度介于衬底和其中形成的掺杂凹坑的均匀区域之间。 中间掺杂的区域由两个凹口边缘附近形成，这些边缘被分开的距离基本上不大于穴袋掺杂的横向扩散长度的两倍。