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    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    1.
    发明授权
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US07547646B2

    公开(公告)日：2009-06-16

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmüller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/31 ,  H01L21/469

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。

    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates
    2.
    发明申请
    Trench capacitor structure and process for applying a covering layer and a mask for trench etching processes in semiconductor substrates 失效
    沟槽电容器结构和用于在半导体衬底中施加用于沟槽蚀刻工艺的覆盖层和掩模的工艺

    公开(公告)号：US20050118777A1

    公开(公告)日：2005-06-02

    申请号：US10974797

    申请日：2004-10-28

    申请人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    发明人： Henry Bernhardt ,  Michael Stadtmuller ,  Olaf Storbeck ,  Stefan Kainz

    IPC分类号： H01L21/20 ,  H01L21/308 ,  H01L21/31 ,  H01L21/314 ,  H01L21/318 ,  H01L21/334 ,  H01L21/469 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

    CPC分类号： H01L27/10861 ,  H01L21/3081 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/1087 ,  H01L29/66181

    摘要： A stress relief layer between a single-crystal semiconductor substrate and a deposited silicon nitride layer or pad nitride is formed from thermally produced silicon nitride. The stress relief layer made from thermally produced silicon nitride replaces a silicon dioxide layer or pad oxide which is customary at this location for example in connection with mask layers. After patterning of a mask, which includes a protective layer portion formed from deposited silicon nitride, the material which is provided according to the invention for the stress relief layer reduces the restrictions imposed for subsequent process steps, such as for example wet-etching steps, acting both on the semiconductor substrate or structures in the semiconductor substrate and also on the stress relief layer. The thermal nitriding is advantageously incorporated into a preanneal step for expelling oxygen from the semiconductor substrate, so that the semiconductor substrate is protected from the etching action of the expelled oxygen by the stress relief layer which is formed, there is no need for an additional temporary etching protection layer for the semiconductor substrate and the overall processing is streamlined.

    摘要翻译： 单晶半导体衬底和沉积的氮化硅层或衬垫氮化物之间的应力消除层由热生产的氮化硅形成。 由热产生的氮化硅制成的应力消除层代替例如与掩模层结合在该位置上通常的二氧化硅层或焊盘氧化物。 在包括由沉积的氮化硅形成的保护层部分的掩模图案化之后，根据本发明为应力消除层提供的材料减少了对随后的工艺步骤施加的限制，例如湿蚀刻步骤， 在半导体衬底或半导体衬底中的结构以及应力消除层上均起作用。 热氮化有利地结合到用于从半导体衬底排出氧的预退火步骤中，使得半导体衬底被形成的应力消除层免受排出的氧的蚀刻作用，不需要额外的临时 用于半导体衬底的蚀刻保护层和整体处理被简化。

    Memory and method for fabricating it
    10.
    发明申请
    Memory and method for fabricating it 审中-公开
    记忆及其制作方法

    公开(公告)号：US20060275981A1

    公开(公告)日：2006-12-07

    申请号：US11442602

    申请日：2006-05-30

    申请人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    发明人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

    摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

    摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。