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    Memory and method for fabricating it
    1.
    发明申请
    Memory and method for fabricating it 审中-公开
    记忆及其制作方法

    公开(公告)号：US20060275981A1

    公开(公告)日：2006-12-07

    申请号：US11442602

    申请日：2006-05-30

    申请人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    发明人： Alejandro Avellan ,  Matthias Goldbach ,  Thomas Hecht ,  Stefan Jakschik ,  Andreas Orth ,  Uwe Schroder ,  Michael Stadtmueller ,  Olaf Storbeck

    IPC分类号： H01L21/8242 ,  H01L29/94

    CPC分类号： H01L29/66181 ,  H01L27/10829 ,  H01L27/10867

    摘要： Memory and method for fabricating it A memory formed as an integrated circuit in a semiconductor substrate and having storage capacitors and switching transistors. The storage capacitors are formed in the semiconductor substrate in a trench and have an outer electrode layer, which is formed around the trench, a dielectric intermediate layer, which is embodied on the trench wall, and an inner electrode layer, with which the trench is essentially filled, and the switching transistors are formed in the semiconductor substrate in a surface region and have a first source/drain doping region, a second source/drain doping region and an intervening channel, which is separated from a gate electrode by an insulator layer.

    摘要翻译： 存储器及其制造方法在半导体衬底中形成为集成电路并具有存储电容器和开关晶体管的存储器。 存储电容器形成在沟槽中的半导体衬底中，并且具有围绕沟槽形成的外部电极层，体现在沟槽壁上的电介质中间层和内部电极层，沟槽是 基本上填充，并且开关晶体管形成在表面区域中的半导体衬底中，并且具有第一源极/漏极掺杂区域，第二源极/漏极掺杂区域和中间沟道，其通过绝缘体层与栅电极分离 。

    Method for fabricating microchips using metal oxide masks
    4.
    发明授权
    Method for fabricating microchips using metal oxide masks 有权
    使用金属氧化物掩模制造微芯片的方法

    公开(公告)号：US07268037B2

    公开(公告)日：2007-09-11

    申请号：US11040091

    申请日：2005-01-24

    申请人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

    发明人： Stefan Jakschik ,  Thomas Hecht ,  Uwe Schröder ,  Matthias Goldbach

    IPC分类号： H01L21/8242

    CPC分类号： H01L27/1087 ,  H01L21/31111 ,  H01L21/3141 ,  H01L21/31616 ,  H01L29/66181

    摘要： A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

    摘要翻译： 用于修改半导体部分的方法包括覆盖这些部分以保持不掺杂金属氧化物，例如氧化铝。 然后，在未被氧化铝覆盖的那些部分中，例如从气相掺杂半导体。 最后，再次选择性地除去氧化铝，例如使用热磷酸。 由硅，氧化硅或氮化硅形成的半导体表面的部分保留在晶片上。

    Charge-trapping memory device and method of production
    5.
    发明授权
    Charge-trapping memory device and method of production 失效
    电荷俘获记忆装置及生产方法

    公开(公告)号：US07132337B2

    公开(公告)日：2006-11-07

    申请号：US11017194

    申请日：2004-12-20

    申请人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

    发明人： Stefan Jakschik ,  Matthias Goldbach ,  Thomas Mikolajick ,  Thomas Hecht

    IPC分类号： H01L21/336

    CPC分类号： H01L29/512 ,  H01L21/28282 ,  H01L29/42348 ,  H01L29/78 ,  H01L29/7923

    摘要： Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

    摘要翻译： 电荷捕获区域布置在栅电极的下边缘下方彼此分离。 源极/漏极区域以相对于电荷俘获区域的自对准方式通过在低能量下的掺杂工艺形成，以形成仅在电荷俘获区域下方仅小的距离的浅结。 自对准确保了大量的编程擦除周期，具有高效率和良好的数据保留，因为注入相反符号的电荷载体的位置被狭义地和精确地定义。

    Semiconductor device and corresponding fabrication method
    9.
    发明授权
    Semiconductor device and corresponding fabrication method 失效
    半导体器件及相应的制造方法

    公开(公告)号：US07045855B2

    公开(公告)日：2006-05-16

    申请号：US10777207

    申请日：2004-02-13

    申请人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

    发明人： Björn Fischer ,  Matthias Goldbach ,  Stefan Jakschik ,  Till Schlösser

    IPC分类号： H01L29/792

    CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/31612 ,  H01L21/31616 ,  H01L27/10823 ,  H01L27/10826 ,  H01L27/10829 ,  H01L27/10838 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10879 ,  H01L28/56 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66181 ,  H01L29/785

    摘要： A semiconductor device having a gate structure, the gate structure having a first gate dielectric made of a first material having a first thickness and a first dielectric constant, which is situated directly above the channel region, and an overlying second gate dielectric made of a second material having a second thickness and a second dielectric constant, which is significantly greater than the first dielectric constant; and the first thickness of the first gate dielectric and the second thickness of the second gate dielectric being chosen such that the corresponding thickness of a gate structure with the first gate dielectric, to obtain the same threshold voltage, is at least of the same magnitude as a thickness equal to the sum of the first thickness and the second thickness. The invention also relates to a corresponding fabrication method.

    摘要翻译： 具有栅极结构的半导体器件，所述栅极结构具有由第一材料制成的第一栅极电介质，所述第一材料具有位于所述沟道区域正上方的第一厚度和第一介电常数，以及由第二栅极电介质构成的覆盖的第二栅极电介质 材料具有明显大于第一介电常数的第二厚度和第二介电常数; 并且第一栅极电介质的第一厚度和第二栅极电介质的第二厚度被选择为使得具有第一栅极电介质的栅极结构的相应厚度以获得相同的阈值电压至少与 厚度等于第一厚度和第二厚度之和的厚度。 本发明还涉及相应的制造方法。