摘要:
Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.
摘要:
Disclosed herein is a clock data recovery circuit including: a first phase detector; a loop filter; a charge pump; a voltage-controlled oscillator; a second phase detector; a phase correction information generation section; and a phase correction information addition section.
摘要:
The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.
摘要:
The present disclosure provides a phase comparator including, a first latch, a second latch, a first detection circuit, a second detection circuit, and a charge-pump circuit having the function of a changeover switch.
摘要:
Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.
摘要:
Disclosed herein is a driver amplifier circuit, including: a first current source transistor of a first conductivity type, and a second current source transistor of the first conductivity type, control voltages being supplied to gates of the first current source transistor and the second current source transistor, respectively; a first switching transistor of the first conductivity type, and a second switching transistor of the first conductivity type; a third switching transistor of a second conductivity type, and a fourth switching transistor of the second conductivity type; first, second, third, and fourth resistor elements; and a first output node and a second output node.
摘要:
Disclosed herein is a CDR circuit including delay elements, including: a divider having a delay element and configured to extract a clock by using, as a trigger, a data input with a signal transition regularly inserted; and a latch configured to latch an input data signal in synchronization with the clock extracted by the divider.
摘要:
Disclosed herein is a driver amplifier circuit, including: a first current source transistor of a first conductivity type, and a second current source transistor of the first conductivity type, control voltages being supplied to gates of the first current source transistor and the second current source transistor, respectively; a first switching transistor of the first conductivity type, and a second switching transistor of the first conductivity type; a third switching transistor of a second conductivity type, and a fourth switching transistor of the second conductivity type; first, second, third, and fourth resistor elements; and a first output node and a second output node.
摘要:
A signal transmission system including: a first connector apparatus, and a second connector apparatus that is coupled with the first connector apparatus. The first connector apparatus and the second connector apparatus are coupled together to form an electromagnetic field coupling unit, and a transmission object signal is converted into a radio signal, which is then transmitted through the electromagnetic field coupling unit, between the first connector apparatus and the second connector apparatus.
摘要:
A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.