公开(公告)号：US08101442B2

公开(公告)日：2012-01-24

申请号：US12390264

申请日：2009-02-20

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

IPC分类号： H01L21/00 ,  H01L21/04 ,  H01L21/14 ,  H01L21/15 ,  H01L31/036

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3262

摘要： A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.

摘要翻译： 安装在EL显示装置上的薄膜晶体管的制造工艺简化。 通过堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜来制造薄膜晶体管; 在堆叠的膜上形成第一抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 在薄膜堆叠体上进行侧蚀刻进行第二蚀刻，形成栅电极层; 以及使用第二抗蚀剂掩模形成源极和漏极电极层等。 使用薄膜晶体管制造EL显示装置。

公开(公告)号：US20090224249A1

公开(公告)日：2009-09-10

申请号：US12390264

申请日：2009-02-20

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Atsushi Umezaki

IPC分类号： H01L29/04 ,  H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3262

摘要： A manufacture process of a thin film transistor mounted on an EL display device is simplified. A thin film transistor is manufactured by stacking a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film; forming a first resist mask over the stacked films; performing first etching to form a thin-film stack body; performing second etching by side etching is conducted on the thin-film stack body to form a gate electrode layer; and forming a source and drain electrode layer and the like with use of a second resist mask. An EL display device is manufactured using the thin film transistor.

摘要翻译： 安装在EL显示装置上的薄膜晶体管的制造工艺简化。 通过堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜来制造薄膜晶体管; 在堆叠的膜上形成第一抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 在薄膜堆叠体上进行侧蚀刻进行第二蚀刻，形成栅电极层; 以及使用第二抗蚀剂掩模形成源极和漏极电极层等。 使用薄膜晶体管制造EL显示装置。

公开(公告)号：US20090152559A1

公开(公告)日：2009-06-18

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US07993991B2

公开(公告)日：2011-08-09

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L21/00 ,  G02F1/136

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US08120030B2

公开(公告)日：2012-02-21

申请号：US12633067

申请日：2009-12-08

申请人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Hiromichi Godo ,  Satoshi Kobayashi ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04

CPC分类号： H01L29/78696 ,  H01L27/12 ,  H01L29/04

摘要： Off current of a bottom gate thin film transistor in which a semiconductor layer is shielded from light by a gate electrode is reduced. A thin film transistor includes a gate electrode layer; a first semiconductor layer; a second semiconductor layer, provided on and in contact with the first semiconductor layer; a gate insulating layer between and in contact with the gate electrode layer and the first semiconductor layer; impurity semiconductor layers in contact with the second semiconductor layer; and source and drain electrode layers partially in contact with the impurity semiconductor layers and the first and second semiconductor layers. The entire surface of the first semiconductor layer on the gate electrode layer side is covered by the gate electrode layer; and a potential barrier at a portion where the first semiconductor layer is in contact with the source or drain electrode layer is 0.5 eV or more.

摘要翻译： 其中半导体层被栅极电极遮挡光的底栅薄膜晶体管的截止电流减小。 薄膜晶体管包括栅电极层; 第一半导体层; 第二半导体层，设置在第一半导体层上并与第一半导体层接触; 在栅极电极层和第一半导体层之间并与之接触的栅极绝缘层; 与第二半导体层接触的杂质半导体层; 以及与杂质半导体层和第一和第二半导体层部分接触的源极和漏极电极层。 栅极电极层侧的第一半导体层的整个表面被栅电极层覆盖; 并且在第一半导体层与源极或漏极电极层接触的部分处的势垒为0.5eV以上。

公开(公告)号：US08624254B2

公开(公告)日：2014-01-07

申请号：US13226775

申请日：2011-09-07

申请人： Yuji Egi ,  Tetsuhiro Tanaka ,  Toshiyuki Isa ,  Hidekazu Miyairi ,  Koji Dairiki ,  Yoichi Kurosawa ,  Kunihiko Suzuki

发明人： Yuji Egi ,  Tetsuhiro Tanaka ,  Toshiyuki Isa ,  Hidekazu Miyairi ,  Koji Dairiki ,  Yoichi Kurosawa ,  Kunihiko Suzuki

IPC分类号： H01L29/04 ,  H01L29/786

CPC分类号： H01L29/78618 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： A highly reliable transistor in which change in electrical characteristics is suppressed is provided. A highly reliable transistor in which change in electrical characteristics is suppressed is manufactured with high productivity. A display device with less image deterioration over time is provided. An inverted staggered thin film transistor which includes, between a gate insulating film and impurity semiconductor films functioning as source and drain regions, a semiconductor stacked body including a microcrystalline semiconductor region and a pair of amorphous semiconductor regions. In the microcrystalline semiconductor region, the nitrogen concentration on the gate insulating film side is low and the nitrogen concentration in a region in contact with the amorphous semiconductor is high. Further, an interface with the amorphous semiconductor has unevenness.

摘要翻译： 提供了其中抑制电特性变化的高度可靠的晶体管。 以高生产率制造其中抑制电特性变化的高度可靠的晶体管。 提供了具有随时间图像劣化的显示装置。 一种倒置交错薄膜晶体管，其包括在栅极绝缘膜和用作源极和漏极区域的杂质半导体膜之间，包括微晶半导体区域和一对非晶半导体区域的半导体层叠体。 在微晶半导体区域中，栅绝缘膜侧的氮浓度低，与非晶半导体接触的区域的氮浓度高。 此外，与非晶半导体的界面具有不均匀性。

公开(公告)号：US09069202B2

公开(公告)日：2015-06-30

申请号：US13407891

申请日：2012-02-29

申请人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

发明人： Hidekazu Miyairi ,  Tetsuji Ishitani ,  Daisuke Kubota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

IPC分类号： G02F1/1343 ,  G02F1/1333 ,  G02F1/1362 ,  G02F1/136

CPC分类号： G02F1/133345 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/124

摘要： Provided are a liquid crystal display device with horizontal electric field mode, in which a decrease in driving speed can be suppressed by reducing the resistance of a wiring even when the number of pixels is increased, and a manufacturing method thereof. One of a scan wiring and a signal wiring is divided in an intersection portion where the scan wiring and the signal wiring intersect with each other, and the separated wirings are connected with a connection electrode positioned over a thick insulating film. Accordingly, parasitic capacitance at the intersection portion can be reduced, preventing the decrease in the driving speed. The connection electrode is formed at the same time as formation of a pixel electrode and a common electrode using a low-resistance metal, which contributes to the reduction in manufacturing process of the liquid crystal display device.

摘要翻译： 提供一种具有水平电场模式的液晶显示装置及其制造方法，其中即使增加像素数也可以通过降低布线的电阻来抑制驱动速度的降低。 扫描布线和信号布线之一被划分在扫描布线和信号布线彼此相交的交叉部分中，并且分离的布线与位于厚绝缘膜上的连接电极连接。 因此，可以减少交叉部分处的寄生电容，防止驱动速度的降低。 连接电极与使用低电阻金属的像素电极和公共电极的形成同时形成，这有助于液晶显示装置的制造工艺的减少。

公开(公告)号：US08637866B2

公开(公告)日：2014-01-28

申请号：US12490447

申请日：2009-06-24

申请人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki ,  Takuya Hirohashi

发明人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki ,  Takuya Hirohashi

IPC分类号： H01L29/72

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, a semiconductor layer which contains nitrogen and includes crystal regions in an amorphous structure between a gate insulating layer and source and drain regions, at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 至少在源区和漏区侧，薄膜晶体管包括作为缓冲层的半导体层，该半导体层含有氮并且包括在栅极绝缘层和源极和漏极区之间的非晶结构中的晶体区域。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US20120229747A1

公开(公告)日：2012-09-13

申请号：US13407891

申请日：2012-02-29

申请人： Hidekazu MIYAIRI ,  Tetsuji Ishitani ,  Dajsuke Kobota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

发明人： Hidekazu MIYAIRI ,  Tetsuji Ishitani ,  Dajsuke Kobota ,  Toshiyuki Isa ,  Kouhei Toyotaka ,  Susumu Kawashima

IPC分类号： G02F1/1333

CPC分类号： G02F1/133345 ,  G02F1/134363 ,  G02F1/136209 ,  G02F1/136213 ,  G02F1/136286 ,  G02F2001/13606 ,  G02F2001/13629 ,  G02F2001/136295 ,  G02F2201/124

摘要： Provided are a liquid crystal display device with horizontal electric field mode, in which a decrease in driving speed can be suppressed by reducing the resistance of a wiring even when the number of pixels is increased, and a manufacturing method thereof. One of a scan wiring and a signal wiring is divided in an intersection portion where the scan wiring and the signal wiring intersect with each other, and the separated wirings are connected with a connection electrode positioned over a thick insulating film. Accordingly, parasitic capacitance at the intersection portion can be reduced, preventing the decrease in the driving speed. The connection electrode is formed at the same time as formation of a pixel electrode and a common electrode using a low-resistance metal, which contributes to the reduction in manufacturing process of the liquid crystal display device.

摘要翻译： 提供一种具有水平电场模式的液晶显示装置及其制造方法，其中即使增加像素数也可以通过降低布线的电阻来抑制驱动速度的降低。 扫描布线和信号布线之一被划分在扫描布线和信号布线彼此相交的交叉部分中，并且分离的布线与位于厚绝缘膜上的连接电极连接。 因此，可以减少交叉部分处的寄生电容，防止驱动速度的降低。 连接电极与使用低电阻金属的像素电极和公共电极的形成同时形成，这有助于液晶显示装置的制造工艺的减少。

公开(公告)号：US08124972B2

公开(公告)日：2012-02-28

申请号：US12429486

申请日：2009-04-24

申请人： Koji Dairiki ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Akiharu Miyanaga ,  Takuya Hirohashi ,  Shunpei Yamazaki ,  Takeyoshi Watabe

发明人： Koji Dairiki ,  Hidekazu Miyairi ,  Toshiyuki Isa ,  Akiharu Miyanaga ,  Takuya Hirohashi ,  Shunpei Yamazaki ,  Takeyoshi Watabe

IPC分类号： H01L29/786

CPC分类号： H01L27/127 ,  H01J37/32091 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.

摘要翻译： 薄膜晶体管包括覆盖栅电极的栅极绝缘层，在具有绝缘表面的基板上; 形成在非晶结构中包含多个晶体区域的沟道形成区域的半导体层; 赋予形成源极区域和漏极区域的一种导电型的杂质半导体层; 以及由位于半导体层和杂质半导体层之间的非晶半导体形成的缓冲层。 薄膜晶体管包括晶体区域，其包括微小晶粒和倒锥形或倒棱锥晶粒，其每一个从远离栅极绝缘层和半导体层之间的界面的位置朝向半导体层的方向大致径向地生长 沉积在不到达杂质半导体层的区域中。