公开(公告)号：US07993991B2

公开(公告)日：2011-08-09

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L21/00 ,  G02F1/136

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US20090152559A1

公开(公告)日：2009-06-18

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L29/786 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US08778745B2

公开(公告)日：2014-07-15

申请号：US13159830

申请日：2011-06-14

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/20 ,  H01L21/36

CPC分类号： H01L21/0262 ,  C23C16/0272 ,  C23C16/45523 ,  C23C16/515 ,  H01L21/0237 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/02532 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78648 ,  H01L29/78678 ,  H01L29/78696

摘要： A method for manufacturing a semiconductor device comprises the steps of forming a seed over the insulating film by introducing hydrogen and a deposition gas into a first treatment chamber under a first condition and forming a microcrystalline semiconductor film over the seed by introducing hydrogen and the deposition gas into a second treatment chamber under a second condition: a second flow rate of the deposition gas is periodically changed between a first value and a second value; and a second pressure in the second treatment chamber is higher than or equal to 1.0×102 Torr and lower than or equal to 1.0×103 Torr.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：通过在第一条件下将氢和沉积气体引入第一处理室中，在绝缘膜上形成晶种，并通过引入氢和沉积气体在晶种上形成微晶半导体膜 在第二条件下进入第二处理室：沉积气体的第二流量在第一值和第二值之间周期性地变化; 并且第二处理室中的第二压力高于或等于1.0×102乇并且小于或等于1.0×10 3乇。

公开(公告)号：US07790483B2

公开(公告)日：2010-09-07

申请号：US12473776

申请日：2009-05-28

申请人： Hidekazu Miyairi ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Ryu Komatsu

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66757

摘要： To provide a manufacturing method of a thin film transistor and a display device with fewer masks than a conventional method. A thin film transistor is manufactured by including the steps of: forming a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film to be stacked; forming a resist mask including three regions with different thicknesses; performing first etching to form a thin-film stack body; performing second etching in which side-etching is performed on the thin-film stack body to form a gate electrode layer; and recessing the resist mask to form a semiconductor layer and a source and drain electrode layer. A resist mask including three regions with different thicknesses can be formed using a four-tone photomask, for example.

摘要翻译： 提供一种薄膜晶体管的制造方法和具有比常规方法更少的掩模的显示装置。 通过包括以下步骤制造薄膜晶体管：形成要堆叠的第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜; 形成包括具有不同厚度的三个区域的抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 进行在薄膜堆叠体上进行侧面蚀刻以形成栅电极层的第二蚀刻; 并使抗蚀剂掩模凹陷以形成半导体层和源极和漏极电极层。 例如，可以使用四色光掩模形成包括具有不同厚度的三个区域的抗蚀剂掩模。

公开(公告)号：US08859404B2

公开(公告)日：2014-10-14

申请号：US13211565

申请日：2011-08-17

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

IPC分类号： C23C16/24 ,  H01L21/20 ,  H01L21/36 ,  H01L21/02 ,  H01L29/786 ,  H01L31/18 ,  H01L31/0368 ,  H01L29/04 ,  H01L29/66

CPC分类号： H01L21/02532 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02502 ,  H01L21/0262 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78648 ,  H01L29/78672 ,  H01L29/78678 ,  H01L29/78696 ,  H01L31/03685 ,  H01L31/068 ,  H01L31/1824 ,  Y02E10/545 ,  Y02E10/547 ,  Y02E10/548 ,  Y02P70/521

摘要： A seed crystal including mixed phase grains having high crystallinity at a low density is formed under a first condition over an insulating film, and then a first microcrystalline semiconductor film is formed over the seed crystal under a second condition that allows the mixed phase grains to grow and a space between the mixed phase grains to be filled. Then, a second microcrystalline semiconductor film is formed over the first microcrystalline semiconductor film under a third condition that allows formation of a microcrystalline semiconductor film having high crystallinity without increasing the space between the mixed phase grains included in the first microcrystalline semiconductor film.

摘要翻译： 在第一条件下，在绝缘膜上形成包含低密度结晶度的混合相的晶种，然后在允许混合晶粒生长的第二条件下在晶种上形成第一微晶半导体膜 以及要填充的混合相颗粒之间的空间。 然后，在允许形成具有高结晶度的微晶半导体膜而不增加包含在第一微晶半导体膜中的混晶相之间的空间的第三条件下，在第一微晶半导体膜上形成第二微晶半导体膜。

公开(公告)号：US20090311809A1

公开(公告)日：2009-12-17

申请号：US12473776

申请日：2009-05-28

申请人： Hidekazu Miyairi ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Ryu Komatsu

IPC分类号： H01L33/00 ,  H01L21/336

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/66757

摘要： To provide a manufacturing method of a thin film transistor and a display device with fewer masks than a conventional method. A thin film transistor is manufactured by including the steps of: forming a first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film to be stacked; forming a resist mask including three regions with different thicknesses; performing first etching to form a thin-film stack body; performing second etching in which side-etching is performed on the thin-film stack body to form a gate electrode layer; and recessing the resist mask to form a semiconductor layer and a source and drain electrode layer. A resist mask including three regions with different thicknesses can be formed using a four-tone photomask, for example.

摘要翻译： 提供一种薄膜晶体管的制造方法和具有比常规方法更少的掩模的显示装置。 通过包括以下步骤制造薄膜晶体管：形成要堆叠的第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜; 形成包括具有不同厚度的三个区域的抗蚀剂掩模; 执行第一蚀刻以形成薄膜堆叠体; 进行在薄膜堆叠体上进行侧面蚀刻以形成栅电极层的第二蚀刻; 并使抗蚀剂掩模凹陷以形成半导体层和源极和漏极电极层。 例如，可以使用四色光掩模形成包括具有不同厚度的三个区域的抗蚀剂掩模。

公开(公告)号：US08426295B2

公开(公告)日：2013-04-23

申请号：US13267257

申请日：2011-10-06

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi ,  Yoshitaka Yamamoto

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi ,  Yoshitaka Yamamoto

IPC分类号： H01L21/336

CPC分类号： H01L29/78696 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/0262 ,  H01L21/28008 ,  H01L29/04 ,  H01L29/6675

摘要： To provide a manufacturing method of a microcrystalline silicon film having both high crystallinity and high film density. In the manufacturing method of a microcrystalline silicon film according to the present invention, a first microcrystalline silicon film that includes mixed phase grains is formed over an insulating film under a first condition, and a second microcrystalline silicon film is formed thereover under a second condition. The first condition and the second condition are a condition in which a deposition gas containing silicon and a gas containing hydrogen are used as a first source gas and a second source gas. The first source gas is supplied under the first condition in such a manner that supply of a first gas and supply of a second gas are alternately performed.

摘要翻译： 提供具有高结晶度和高膜密度的微晶硅膜的制造方法。 在本发明的微晶硅膜的制造方法中，在第一条件下，在绝缘膜上形成包含混晶相的第一微晶硅膜，在第二条件下形成第二微晶硅膜。 第一条件和第二条件是使用含硅和含氢气体的沉积气体作为第一源气体和第二源气体的条件。 在第一条件下以第一气体的供给和第二气体的供给交替进行的方式供给第一源气体。

公开(公告)号：US08299467B2

公开(公告)日：2012-10-30

申请号：US12977479

申请日：2010-12-23

申请人： Hidekazu Miyairi ,  Ryu Komatsu ,  Takafumi Mizoguchi

发明人： Hidekazu Miyairi ,  Ryu Komatsu ,  Takafumi Mizoguchi

IPC分类号： H01L33/16

CPC分类号： H01L29/78696 ,  H01L29/04 ,  H01L29/66757

摘要： A thin film transistor is provided with a high crystallized region in a channel formation region and a high resistance region between a source and a drain, and thus has a high electric effect mobility and a large on current. The thin film transistor includes an “impurity which suppresses generation of crystal nuclei” contained in the base layer or located on its surface, a first wiring layer over a base layer, an impurity semiconductor layer over the first wiring, a semiconductor layer over the impurity semiconductor layer, the semiconductor layer comprises a crystalline region and a region containing an amorphous phase which is formed adjacent to the base layer.

摘要翻译： 薄膜晶体管在沟道形成区域和源极和漏极之间具有高结晶区域，并且因此具有高的电效应迁移率和大的导通电流。 薄膜晶体管包括抑制基底层中或位于其表面上的晶体核的产生的杂质，在基底层上的第一布线层，第一布线上的杂质半导体层，杂质半导体层上的半导体层 ，所述半导体层包括结晶区域和包含与所述基底层相邻形成的非晶相的区域。

公开(公告)号：US08450158B2

公开(公告)日：2013-05-28

申请号：US13282650

申请日：2011-10-27

申请人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

发明人： Ryu Komatsu ,  Yasuhiro Jinbo ,  Hidekazu Miyairi

IPC分类号： H01L21/336 ,  H01L21/365

CPC分类号： H01L21/02532 ,  H01L21/02422 ,  H01L21/0245 ,  H01L21/02513 ,  H01L21/02595 ,  H01L21/0262 ,  H01L29/66765 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/78669 ,  H01L29/78678 ,  Y02A40/29

摘要： A seed crystal which includes mixed phase grains including an amorphous silicon region and a crystallite which is a microcrystal that can be regarded as a single crystal is formed on an insulating film by a plasma CVD method under a first condition that enables mixed phase grains having high crystallinity and high uniformity of grain sizes to be formed at a low density, and then a microcrystalline semiconductor film is formed to be stacked on the seed crystal by a plasma CVD method under a second condition that enables the mixed phase grains to grow to fill a space between the mixed phase grains.

摘要翻译： 在通过等离子体CVD法在绝缘膜上形成包含非晶硅区域的混合相晶粒和作为可以被认为是单晶的微晶的晶种的晶种，其中在第一条件下，使得具有高的 以低密度形成晶粒尺寸的结晶度和高均匀性，然后通过等离子体CVD法在微晶半导体膜上形成层叠在晶种上的第二条件，使得混合相晶粒生长以填充 混合相之间的间隙。

公开(公告)号：US07985605B2

公开(公告)日：2011-07-26

申请号：US12422470

申请日：2009-04-13

申请人： Shigeki Komori ,  Ryu Komatsu

发明人： Shigeki Komori ,  Ryu Komatsu

IPC分类号： H01L21/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L27/3262 ,  H01L2227/323

摘要： A first conductive film, a first insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked in this order (a thin-film stacked body); first etching is performed to expose the first conductive film and form at least a pattern of the thin-film stacked body; second etching is performed to form a pattern of the first conductive film. The second etching is performed under a condition in which the first conductive film is side-etched. Further, after forming the patterns, an EL layer can be formed selectively by utilizing a depression and a projection due to the patterns.

摘要翻译： 依次层叠第一导电膜，第一绝缘膜，半导体膜，杂质半导体膜和第二导电膜（薄膜堆叠体）; 执行第一蚀刻以暴露第一导电膜并形成至少薄膜层叠体的图案; 执行第二蚀刻以形成第一导电膜的图案。 在第一导电膜被侧蚀的条件下进行第二蚀刻。 此外，在形成图案之后，可以通过利用凹陷和由于图案的突起而选择性地形成EL层。