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公开(公告)号：US5175704A
公开(公告)日：1992-12-29
申请号：US607468
申请日：1990-10-31
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
摘要翻译： 在非易失性半导体存储器件中，布线层连接在电源和存储单元之间。 布线层的电阻大于负载晶体管的导通电阻，负载晶体管基本上决定负载特性。 因此，载荷特性曲线在倾斜度上更为平缓，形状更为直线。 这使得数据写入操作对于形成存储单元的制造的晶体管的沟道长度的变化是稳定的。
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2.发明授权Nonvolatile semiconductor memory device with stabilized data write characteristic 失效具有稳定数据写特性的非易失性半导体存储器件
公开(公告)号：US5010520A
公开(公告)日：1991-04-23
申请号：US224953
申请日：1988-07-27
申请人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
发明人： Hidenobu Minagawa , Yuuichi Tatsumi , Hiroshi Iwahashi , Masamichi Asano , Hiroto Nakai , Mizuho Imai
摘要： In a nonvolatile semiconductor memory device, a wiring layer is connected between a power source and a memory cell. Resistance of the wiring layer is larger than the on-resistance of a load transistor, so that the load transistor substantially determines the load characteristic. Therefore, the load characteristic curve is more gentle in inclination and more rectilinear in shape. This makes the data writing operation stable against a variance in the channel lengths of manufactured transistors forming the memory cells.
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公开(公告)号：US4916334A
公开(公告)日：1990-04-10
申请号：US226312
申请日：1988-07-29
摘要： A semiconductor integrated circuit includes a CMOS circuit operated on a voltage of a first voltage level to set an output node thereof to a voltage of the first voltage level or a reference voltage; an output circuit for controlling supply of a voltage of a second voltage level which is higher than the first voltage level to a signal output node; and an isolation MOS transistor having a current path connected between the output node of the CMOS circuit and the signal output node and a gate connected to receive a control signal. The output node of the CMOS circuit is set to the reference voltage with the conduction resistance of the isolation MOS transistor kept high after the lapse of period in which the voltage of the second voltage level is kept supplied to the signal output node. After this, the conduction resistance of the isolation MOS transistor is reduced in response to the control signal.
摘要翻译： 半导体集成电路包括以第一电压电平工作的CMOS电路，以将其输出节点设置为第一电压电平或参考电压的电压; 输出电路，用于控制向信号输出节点提供高于第一电压电平的第二电压电平的电压; 以及隔离MOS晶体管，其具有连接在CMOS电路的输出节点和信号输出节点之间的电流路径以及连接以接收控制信号的栅极。 CMOS电路的输出节点被设定为参考电压，其中隔离MOS晶体管的导通电阻保持高电平，其中第二电压电平的电压被保持提供给信号输出节点。 此后，隔离MOS晶体管的导通电阻响应于控制信号而减小。
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公开(公告)号：US4967394A
公开(公告)日：1990-10-30
申请号：US241748
申请日：1988-09-08
CPC分类号： G11C29/50012 , G11C16/08 , G11C16/28 , G11C16/32 , G11C16/34 , G11C29/24 , G11C29/50 , G11C29/52 , G11C16/04
摘要： A semiconductor memory device in which data can be read out in response to an address signal comprises power source lines, a plurality of row and column conductive lines, a memory cell array including nonvolatile memory cells arranged in a matrix form of rows and columns and respectively connected to the plurality of row and column lines and the power source lines, a first selector circuit for generating a signal for selecting the row conductive lines in response to an address signal, a dummy row line, and a dummy memory cells each having a source, a drain and a control gate connected to the dummy row line. In the semiconductor memory device, one of paths between the source and the power source line and between the drain and the corresponding row line is closed and the other path is opened, and it further includes a second selector circuit for selectively generating a line selection signal for selecting one of the row conductive lines in response to an address signal and a dummy selection signal for selecting the dummy row line in response to the same address signal.
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公开(公告)号：US4882507A
公开(公告)日：1989-11-21
申请号：US226307
申请日：1988-07-29
IPC分类号： G11C11/417 , G11C7/10 , G11C7/22 , G11C11/409 , G11C17/18 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0175 , H03K19/0185
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , H03K19/00361
摘要： A semiconductor integrated circuit includes an output circuit and a control circuit for controlling the output circuit. The control circuit controls the output circuit so as to charge or discharge a preset node in the output circuit at a rate different from an ordinary charging or discharging rate for a preset period of time after a control signal has been changed in level.
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公开(公告)号：US4858192A
公开(公告)日：1989-08-15
申请号：US225510
申请日：1988-07-28
CPC分类号： G11C29/781
摘要： A semiconductor memory device has a redundancy circuit for compensating a defective bit when it occurs in the main memory cells. The redundancy circuit includes spare memory cells, a spare row decoder for selecting the spare memory cells, a first circuit section for inhibiting the use of the main row decoder when the spare row decoder is used, and a second circuit section for selecting the spare row decoder when an address specifying the main row line connected to the defective memory cell is denoted.
摘要翻译： 半导体存储器件具有用于在发生在主存储器单元中时补偿有缺陷的位的冗余电路。 冗余电路包括备用存储单元，用于选择备用存储单元的备用排解码器，当使用备用行解码器时禁止使用主行解码器的第一电路部分和用于选择备用行的第二电路部分 解码器，当指定连接到有缺陷的存储单元的主行线的地址被表示时。
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7.发明授权Semiconductor memory device having transfer gates which prevent high voltages from being applied to memory and dummy cells in the reading operation 失效具有在读取操作中防止高电压施加到存储器和虚设单元的传输门的半导体存储器件
公开(公告)号：US5138579A
公开(公告)日：1992-08-11
申请号：US632613
申请日：1990-12-26
CPC分类号： G11C16/28
摘要： A semiconductor memory device includes word lines selectively driven by a signal from a row decoder, memory cells connected to word lines, first and second data lines, a bit line connected to receive data from the memory cell and to supply received data to the first data lines, dummy cells connected to word lines, first and second dummy data lines, a dummy bit lines connected to receive data from the dummy memory cell and to supply received data to the first dummy data line, a data sensing circuit for generating an output signal corresponding to a potential difference between the second data line and second dummy data line, a first MOS transistor connected between the first and second data lines, a first load circuit for charging the second data line, a second MOS transistor connected between the first and second dummy data lines, and a second load circuit for charging the second dummy data lines. The memory device further includes a first equalizer circuit connected between the second data line and dummy data line and equalizing potentials at both ends during a predetermined period of time after the semiconductor memory device is set in the active mode, and a second equalizer circuit connected between the data line and dummy data line and equalizing potential as at both ends during a predetermined period of time after the memory device is set in the active mode.
摘要翻译： 半导体存储器件包括由来自行解码器的信号选择性地驱动的字线，连接到字线的存储器单元，第一和第二数据线，连接到从存储器单元接收数据并将接收到的数据提供给第一数据的位线 连接到字线的虚拟单元，第一和第二虚拟数据线，连接成从虚拟存储单元接收数据并将接收到的数据提供给第一虚拟数据线的虚拟位线;数据感测电路，用于产生输出信号 对应于第二数据线和第二虚拟数据线之间的电位差，连接在第一和第二数据线之间的第一MOS晶体管，用于对第二数据线充电的第一负载电路，连接在第一和第二数据线之间的第二MOS晶体管 虚拟数据线，以及用于对第二虚拟数据线进行充电的第二负载电路。 存储装置还包括连接在第二数据线和虚拟数据线之间的第一均衡器电路，并且在半导体存储器件被设置为激活模式之后的预定时间段期间使两端的电位相等，以及第二均衡器电路 数据线和虚拟数据线，并且在存储器件被设置为活动模式之后的预定时间段期间两端的均衡电位。
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公开(公告)号：US4611301A
公开(公告)日：1986-09-09
申请号：US597351
申请日：1984-04-06
CPC分类号： G11C16/28
摘要： Data is read out from memory cells in which "0" level and "1" level binary data have been stored, and a signal potential responsive to the readout data is compared with a comparison potential by a sense amplifier, thereby sensing the data. In a comparison potential generator, the above comparison potential is set to have the intermediate potential between a potential obtained by a dummy cell in which the "1" level data has been stored, and a potential obtained by a dummy cell in which the "0" level data has been stored.
摘要翻译： 从存储有“0”电平和“1”电平二进制数据的存储单元中读出数据，并且通过读出放大器将响应于读出数据的信号电位与比较电位进行比较，从而感测数据。 在比较电位发生器中，上述比较电位被设定为具有由存储了“1”电平数据的虚拟单元获得的电位与通过虚拟单元获得的电位之间的中间电位，其中“0” “级别数据已被存储。
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公开(公告)号：US4697101A
公开(公告)日：1987-09-29
申请号：US645392
申请日：1984-08-29
申请人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
发明人： Hiroshi Iwahashi , Masamichi Asano , Masaki Momodomi , Hidenobu Minagawa , Kazuto Suzuki , Akira Narita
IPC分类号： G11C16/12 , G11C16/30 , H03K19/096 , G06F7/38 , H03K17/16
摘要： A semiconductor integrated circuit which has a CMOS inverter formed of p- and n-channel MOSFETs, and a D-type n-channel MOSFET coupled at the gate to the output terminal of the CMOS inverter, having one end coupled to a high voltage terminal and the other end coupled to the drain of the p-channel MOSFET.
摘要翻译： 一种半导体集成电路，其具有由p-沟道MOSFET和n沟道MOSFET形成的CMOS反相器，以及在栅极处连接到CMOS反相器的输出端的D型n沟道MOSFET，其一端耦合到高电压端子 另一端耦合到p沟道MOSFET的漏极。
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10.发明授权
公开(公告)号：US4819212A
公开(公告)日：1989-04-04
申请号：US50717
申请日：1987-05-18
申请人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
发明人： Hiroto Nakai , Hiroshi Iwahashi , Masamichi Asano , Isao Sato , Shigeru Kumagai , Kazuto Suzuki
摘要： A nonvolatile semiconductor memory device includes a memory cell array including a plurality of memory cells each including a nonvolatile transistor, a plurality of row lines each connected to the memory cells arranged on a corresponding row, a plurality of column lines connected to the memory cells arranged on a corresponding column, an address buffer circuit for receiving external address signals at its address input terminal and for outputting internal address signals in response to the received external address signals, column line-select transistors connected to the column lines, a column-decoding circuit for selectively biasing the column line-select transistors, a row-decoding circuit for selectively biasing the row lines, and data-detecting circuit for detecting the potential of the column line selected by the column line-select transistor. The device further includes a control unit generating a control signal for controlling the address buffer circuit so that the internal address signal is set at a predetermined value, to set all the row lines in a non-selected state, thereby setting a column line, selected by the column line-select transistor, at a predetermined potential.
摘要翻译： 非易失性半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储单元，每个存储单元包括非易失性晶体管，多个行线，各行连接到布置在相应行上的存储器单元，多个列线连接到布置的存储单元 在对应的列上，地址缓冲电路，用于在其地址输入端接收外部地址信号，并响应于所接收的外部地址信号输出内部地址信号，连接到列线的列线选择晶体管，列解码电路 用于选择性地偏置列线选择晶体管，用于选择性地偏置行线的行解码电路，以及用于检测由列线选择晶体管选择的列线的电位的数据检测电路。 该装置还包括控制单元，其产生用于控制地址缓冲电路的控制信号，使得内部地址信号被设置为预定值，以将所有行线设置为未选择状态，从而设置列线 通过列线选择晶体管，以预定电位。
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