公开(公告)号：US07439621B1

公开(公告)日：2008-10-21

申请号：US09707844

申请日：2000-11-08

申请人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L23/34 ,  H01L23/552

CPC分类号： H01L23/552 ,  H01L27/0207 ,  H01L27/088 ,  H01L2223/6644 ,  H01L2924/0002 ,  H01L2924/00

摘要： The RF device of the present invention includes: a semiconductor substrate; and first and second semiconductor components provided on the substrate. Each of the components includes source electrodes, a gate electrode and a drain electrode. And multiple through holes, which pass through the substrate in the thickness direction, are opened in a region of the substrate between the two components. To enhance the effect of suppressing electrical interference between the components, a gap between two adjacent ones of the through holes is preferably smaller than the thickness of the substrate.

摘要翻译： 本发明的RF器件包括：半导体衬底; 以及设置在基板上的第一和第二半导体部件。 每个组件包括源电极，栅电极和漏电极。 并且在两个部件之间的基板的区域中打开穿过基板的厚度方向上的多个通孔。 为了增强抑制部件之间的电气干扰的效果，两个相邻的通孔之间的间隙优选小于基板的厚度。

公开(公告)号：US06365513B1

公开(公告)日：2002-04-02

申请号：US09162232

申请日：1998-09-29

申请人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

发明人： Hidetoshi Furukawa ,  Atsushi Noma ,  Tsuyoshi Tanaka ,  Hidetoshi Ishida ,  Daisuke Ueda

IPC分类号： H01L2166

CPC分类号： H01L21/76898 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A via hole having a bottom is formed in a substrate and then a conductor layer is formed at least over a sidewall of the via hole. Thereafter, the substrate is thinned by removing a portion of the substrate opposite to another portion of the substrate in which the via hole is formed such that the conductor layer is exposed.

摘要翻译： 在衬底中形成具有底部的通孔，然后在通孔的至少一个侧壁上形成导体层。 此后，通过去除衬底的与形成通孔的衬底的另一部分相对的部分使得导体层暴露而使衬底变薄。

公开(公告)号：US6166429A

公开(公告)日：2000-12-26

申请号：US33240

申请日：1998-03-03

申请人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Daisuke Ueda

发明人： Hidetoshi Ishida ,  Kazuo Miyatsuji ,  Daisuke Ueda

IPC分类号： H01L23/12 ,  H01L23/495 ,  H01L23/50 ,  H01L23/522 ,  H01L23/48

CPC分类号： H01L23/49503 ,  H01L23/522 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/10161 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599

摘要： A semiconductor device has the following structure: a lead frame 2 is disposed on the center of a package 1, signal terminal electrodes 3 through 7 are disposed on edges of the package, a semiconductor chip 8 is mounted on the lead frame 2, a grounding electrode 16 having a grounding potential is disposed between the signal terminal electrodes 4 and 5, and a grounding electrode having a grounding potential is disposed between the signal terminal electrodes 5 and 6. This structure increases an electrical separation between the signal terminal electrodes.

摘要翻译： 半导体器件具有以下结构：引线框架2设置在封装1的中心，信号端子电极3至7设置在封装的边缘上，半导体芯片8安装在引线框架2上，接地 具有接地电位的电极16设置在信号端子电极4和5之间，并且具有接地电位的接地电极设置在信号端子电极5和6之间。这种结构增加了信号端子电极之间的电气间隔。

公开(公告)号：US20100097105A1

公开(公告)日：2010-04-22

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03B1/00 ,  H01L29/20 ,  H01L29/24 ,  H01L29/772 ,  H03K17/56

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US08203376B2

公开(公告)日：2012-06-19

申请号：US12445390

申请日：2007-11-20

申请人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tatsuo Morita ,  Manabu Yanagihara ,  Hidetoshi Ishida ,  Yasuhiro Uemoto ,  Hiroaki Ueno ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H03K17/687

CPC分类号： H01L29/7787 ,  H01L27/0605 ,  H01L29/0619 ,  H01L29/1066 ,  H01L29/2003 ,  H01L29/432 ,  H01L29/739 ,  H01L29/8124

摘要： A semiconductor device includes a semiconductor layer stack 13 formed on a substrate 11 and having a channel region, a first electrode 16A and a second electrode 16B formed spaced apart from each other on the semiconductor layer stack 13, a first gate electrode 18A formed between the first electrode 16A and the second electrode 16B, and a second gate electrode 18B formed between the first gate electrode 18A and the second electrode 16B. A first control layer 19A having a p-type conductivity is formed between the semiconductor layer stack 13 and the first gate electrode 18A.

摘要翻译： 半导体器件包括形成在衬底11上并具有沟道区的半导体层堆叠13，在半导体层叠层13上彼此隔开形成的第一电极16A和第二电极16B，形成在第一栅电极18A之间的第一栅电极18A 第一电极16A和第二电极16B，以及形成在第一栅电极18A和第二电极16B之间的第二栅电极18B。 在半导体层堆叠13和第一栅电极18A之间形成具有p型导电性的第一控制层19A。

公开(公告)号：US06649463B2

公开(公告)日：2003-11-18

申请号：US09754308

申请日：2001-01-05

申请人： Yukio Iwasaki ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Yukio Iwasaki ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L2120

CPC分类号： H01C17/23 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.

摘要翻译： 调节电阻网络包括彼此并联连接的多个电阻器。 这些电阻器中的每一个可通过照射光而被切割，并且通过切断至少一个电阻来调整调节电阻网络的电阻值。

公开(公告)号：US06201288B1

公开(公告)日：2001-03-13

申请号：US09432107

申请日：1999-11-02

申请人： Yukio Iwasaki ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Yukio Iwasaki ,  Hidetoshi Furukawa ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L2900

CPC分类号： H01C17/23 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

摘要： A regulating resistor network includes a plurality of resistors connected in parallel to each other. Each of these resistors is cuttable by being irradiated with light, and a resistance value of the regulating resistor network is adjustable by cutting at least one of the resistors off.

公开(公告)号：US07656010B2

公开(公告)日：2010-02-02

申请号：US11898958

申请日：2007-09-18

申请人： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L23/58

CPC分类号： H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.

摘要翻译： 半导体器件包括：半导体层; 形成在与半导体层接触的半导体层上的至少一个电极; 以及覆盖半导体层和电极的顶表面的至少一部分的钝化膜，以保护半导体层并由多个子膜形成。 钝化膜包括由氮化铝制成的第一子膜。

公开(公告)号：US07064359B2

公开(公告)日：2006-06-20

申请号：US10912567

申请日：2004-08-06

申请人： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Hidetoshi Ishida ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/42316 ,  H01L29/2003 ,  H01L29/7787 ,  Y10S257/918

摘要： A switching semiconductor device includes a first compound layer formed on a single crystal substrate which includes silicon carbide or sapphire, and including a general formula InxGa1-xN, where 0≦x≦1; a second compound layer formed on the first compound layer, and including a general formula InyALzGa1-y-zN, where 0≦y≦1 and 0

摘要翻译： 开关半导体器件包括形成在包括碳化硅或蓝宝石的单晶衬底上的第一复合层，并且包括通式为N 1 Ga 1-x N，其中 0 <= x <= 1; 形成在第一化合物层上的第二化合物层，并且包含通式为Y 1，Y z，Ga 1-y z N，其中0 < = y <= 1，0

公开(公告)号：US07859087B2

公开(公告)日：2010-12-28

申请号：US12637240

申请日：2009-12-14

申请人： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

发明人： Tomohiro Murata ,  Hiroaki Ueno ,  Hidetoshi Ishida ,  Tetsuzo Ueda ,  Yasuhiro Uemoto ,  Tsuyoshi Tanaka ,  Daisuke Ueda

IPC分类号： H01L23/58

CPC分类号： H01L29/7787 ,  H01L23/367 ,  H01L23/3677 ,  H01L29/2003 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes: a semiconductor layer; at least one electrode formed on a semiconductor layer to be in contact with the semiconductor layer; and a passivation film covering the semiconductor layer and at least part of the top surface of the electrode to protect the semiconductor layer and formed of a plurality of sub-films. The passivation film includes a first sub-film made of aluminum nitride.