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    Bit-line drive circuit for a semiconductor memory
    3.
    发明授权
    Bit-line drive circuit for a semiconductor memory 失效
    半导体存储器的位线驱动电路

    公开(公告)号：US5398201A

    公开(公告)日：1995-03-14

    申请号：US53330

    申请日：1993-04-28

    申请人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

    发明人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/34

    CPC分类号： G11C7/1057 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

    摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

    摘要翻译： 一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。 根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流 只有写入位线才能连接。 根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。 此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。 还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

    Memory cell and a memory device having reduced soft error
    6.
    发明授权
    Memory cell and a memory device having reduced soft error 失效
    存储单元和具有降低的软错误的存储器件

    公开(公告)号：US5523966A

    公开(公告)日：1996-06-04

    申请号：US530421

    申请日：1995-09-18

    申请人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    发明人： Youji Idei ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Toru Masuda ,  Kunihiko Yamaguchi ,  Kenichi Ohhata ,  Takeshi Kusunoki

    IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

    CPC分类号： G11C11/4125 ,  H01L27/11 ,  H01L27/1104

    摘要： Disclosed is a static type memory cell with high immunity from alpha ray-induced soft errors. The memory cell has a coupling capacitance C.sub.c between two data storage nodes 1 and 2. The p-well (or p-substrate) in which the driver-MOS transistors MN3, MN4 and the transfer MOS transistors MN1, MN2 are formed is connected to a V.sub.bb generator. The voltage V.sub.bb is set lower than the low level V.sub.L of the memory cell signal potential. Even when the potential variation .DELTA.V.sub.L of the low-voltage side node 2 is large, the parasitic diode present between the n-type diffusion layer corresponding to the source or drain of MN1-MN4 and the p-well (or p-substrate) does not turn on. Erroneous operations can therefore be prevented.

    摘要翻译： 公开了一种具有高抗α射线诱导的软错误免疫力的静态型记忆体。 存储单元在两个数据存储节点1和2之间具有耦合电容Cc。其中形成驱动器MOS晶体管MN3，MN4和传输MOS晶体管MN1，MN2的p阱（或p衬底）连接到 一个Vbb发生器。 电压Vbb被设定为低于存储单元信号电位的低电平VL。 即使当低电压侧节点2的电位变化量DELTA VL大时，存在于与MN1-MN4的源极或漏极对应的n型扩散层与p阱（或p-衬底）之间的寄生二极管， 不打开 因此可以防止错误的操作。

    Semiconductor memory device having a controlled auxiliary decoder
    7.
    发明授权
    Semiconductor memory device having a controlled auxiliary decoder 失效
    具有受控辅助解码器的半导体存储器件

    公开(公告)号：US5402377A

    公开(公告)日：1995-03-28

    申请号：US243908

    申请日：1994-05-17

    申请人： Kenichi Ohhata ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Youji Idei ,  Takeshi Kusunoki ,  Toru Masuda

    发明人： Kenichi Ohhata ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Youji Idei ,  Takeshi Kusunoki ,  Toru Masuda

    IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C8/00

    CPC分类号： G11C29/70

    摘要： A semiconductor memory device has a primary memory cell array, a primary decoder having a first circuit producing an intermediate signal from an address signal and a second circuit producing a first cell selection signal from the intermediate signal for selectively driving a word line and a bit line, an auxiliary memory cell array having a plurality of memory cells, each being used for a defective memory cell found in the primary memory cell array, an auxiliary decoder connected to the primary decoder to receive the intermediate signal, a non-volatile memory for storing first information indicating that the primary memory cell array contains a defective memory cell from which a cell defect signal is produced and for storing second information indicating an address of the defective memory cell from which a defective cell address signal is produced, and a control circuit responsive to the cell defect signal and the defective cell address signal for producing a first control signal to be supplied to the second circuit and a second control signal to be supplied to the auxiliary decoder. The primary decoder is prohibited by the first control signal from accessing a defective memory cell having an address represented by the defective cell address signal. The auxiliary decoder produces a second cell selection signal from the intermediate signal under control of the second control signal and of the cell defect signal for selectively accessing a memory cell in the auxiliary memory cell array.

    摘要翻译： 半导体存储器件具有主存储单元阵列，主解码器具有产生来自地址信号的中间信号的第一电路和从该中间信号产生第一单元选择信号的第二电路，用于选择性地驱动字线和位线 ，具有多个存储单元的辅助存储单元阵列，每个存储单元用于存储在主存储单元阵列中的缺陷存储单元，连接到主解码器以接收中间信号的辅助解码器，用于存储的非易失性存储器 指示主存储单元阵列包含产生单元缺陷信号的缺陷存储单元的第一信息，以及用于存储表示产生有缺陷单元地址信号的缺陷存储单元的地址的第二信息，以及响应于控制电路的控制电路 到单元缺陷信号和用于产生第一控制信号的有缺陷单元地址信号 提供给第二电路和第二控制信号以提供给辅助解码器。 主解码器被第一控制信号禁止访问具有由缺陷单元地址信号表示的地址的有缺陷的存储单元。 辅助解码器在第二控制信号和单元缺陷信号的控制下，从中间信号产生第二单元选择信号，用于选择性地访问辅助存储单元阵列中的存储单元。

    High-speed static random access memory
    8.
    发明授权
    High-speed static random access memory 有权
    高速静态随机存取存储器

    公开(公告)号：US6075729A

    公开(公告)日：2000-06-13

    申请号：US145161

    申请日：1998-09-01

    申请人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

    发明人： Kenichi Ohhata ,  Fumihiko Arakawa ,  Takeshi Kusunoki ,  Hiroaki Nambu ,  Kazuo Kanetani ,  Kaname Yamasaki ,  Keiichi Higeta

    IPC分类号： G11C7/12 ,  G11C11/412 ,  G11C7/00

    CPC分类号： G11C11/412 ,  G11C7/12 ,  G11C2207/12

    摘要： A semiconductor memory has a plurality of word lines a plurality of bit line pairs and a plurality of memory cells formed at intersection points between the word lines and the bit line pairs. A word decoder generates a word line select signal upon receipt of an address signal and a bit decoder generates a bit line select signal on receiving the address signal. A bit line load circuit receives a signal current from the applicable memory cell, a sense circuit detects an output signal from the bit line load circuit, and a bit line pull-down circuit and a bit line recovery circuit drives the applicable bit lines upon writing data to the memory cell in question. The bit line load circuit and the bit line recovery circuit include pMOS transistors whose drains are connected to the bit lines and whose gates are fed with a control signal, and diodes whose anodes are connected to a first power supply and whose cathodes are connected to sources of the pMOS transistors, the pMOS transistors and the diodes being furnished to each of the bit line pairs. The pMOS transistors are inhibited from conducting while the bit lines are being driven Low by the bit line pull-down circuit during a write cycle, and allowed to conduct during other periods including a read cycle. This constitution shortens the recovery time, implementing a high-speed SRAM with a shortened cycle time.

    摘要翻译： 半导体存储器具有多个字线，多个位线对和形成在字线和位线对之间的交点处的多个存储单元。 字解码器在接收到地址信号时产生字线选择信号，并且位解码器在接收到地址信号时产生位线选择信号。 位线负载电路从可应用的存储单元接收信号电流，感测电路检测来自位线负载电路的输出信号，位线下拉电路和位线恢复电路在写入时驱动可应用的位线 数据到所讨论的存储单元。 位线负载电路和位线恢复电路包括其漏极连接到位线并且其栅极被馈送控制信号的pMOS晶体管，以及其阳极连接到第一电源并且其阴极连接到源极的二极管 的pMOS晶体管，pMOS晶体管和二极管被提供给每个位线对。 在写周期期间位线被位线下拉电路驱动为低电平时，禁止pMOS晶体管导通，并允许其在包括读周期的其他周期期间导通。 这种结构缩短了恢复时间，实现了一个缩短周期时间的高速SRAM。

    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
    9.
    发明授权
    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
    集成电路中使用的半导体集成电路和半导体逻辑电路

    公开(公告)号：US06369617B1

    公开(公告)日：2002-04-09

    申请号：US09437268

    申请日：1999-11-10

    申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    IPC分类号： G11C800

    CPC分类号： G11C8/10

    摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit include a semiconductor logic circuit wherein the number of columns of transistors for pulling down an output node is small even if the number of inputs is large, and the true output signal and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. By virtue of this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, the reduction of access time and power consumption and the increase of the cycles are enabled.

    摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主解码器都包括半导体逻辑电路，其中列数 用于下拉输出节点的晶体管即使输入数量大也很小，并且获得具有大致相同延迟时间的真实输出信号和互补输出信号，并且解码器电路中的每个电路的输出脉冲长度为 减少 通过这种布置，解码器电路的工作可以加快，可以降低功耗，可以提高周期，并且在半导体存储器中，例如可以减少访问时间和功耗，并且增加 的周期被启用。

    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit
    10.
    发明授权
    Semiconductor integrated circuit and semiconductor logic circuit used in the integrated circuit 失效
    集成电路中使用的半导体集成电路和半导体逻辑电路

    公开(公告)号：US06998878B2

    公开(公告)日：2006-02-14

    申请号：US10754596

    申请日：2004-01-12

    申请人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    发明人： Kazuo Kanetani ,  Hiroaki Nambu ,  Kaname Yamasaki ,  Takeshi Kusunoki ,  Keiichi Higeta ,  Kunihiko Yamaguchi ,  Fumihiko Arakawa

    IPC分类号： H03K19/20

    CPC分类号： G11C8/10

    摘要： To speed up the operation of a decoder circuit, reduce the power consumption of the decoder circuit and increase the cycle, each circuit such as a buffer, a predecoder and a main decoder in the decoder circuit includes a semiconductor logic circuit in which the number of columns of transistors for pulling down at an output node is small, even if the number of inputs is many and the true and a complementary output signal having approximately the same delay time are acquired and the output pulse length of each circuit in the decoder circuit is reduced. With this arrangement, the operation of the decoder circuit can be sped up, the power consumption can be reduced, the cycles can be increased and, in a semiconductor memory, for example, access time and power consumption can be reduced and the cycles can be increased.

    摘要翻译： 为了加速解码器电路的运行，降低解码器电路的功耗并增加周期，解码器电路中的每个电路如缓冲器，预解码器和主译码器都包括半导体逻辑电路，其中， 在输出节点下拉的晶体管列很小，即使输入数量很多，并且获得了真实的和具有大致相同延迟时间的互补输出信号，并且解码器电路中每个电路的输出脉冲长度是 减少 利用这种布置，可以加速解码器电路的操作，可以降低功耗，可以提高周期，例如，在半导体存储器中，可以减少访问时间和功耗，并且可以将周期 增加。