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34 条记录 (耗时 0.046 秒)

    Bit-line drive circuit for a semiconductor memory
    1.
    发明授权
    Bit-line drive circuit for a semiconductor memory 失效
    半导体存储器的位线驱动电路

    公开(公告)号：US5398201A

    公开(公告)日：1995-03-14

    申请号：US53330

    申请日：1993-04-28

    申请人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

    发明人： Hiroaki Nambu ,  Noriyuki Homma ,  Kunihiko Yamaguchi ,  Hisayuki Higuchi ,  Kazuo Kanetani ,  Youji Idei ,  Ken'ichi Ohata ,  Yoshiaki Sakurai ,  Masanori Odaka ,  Goro Kitsukawa

    IPC分类号： G11C5/14 ,  G11C7/10 ,  G11C11/34

    CPC分类号： G11C7/1057 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

    摘要： A circuit technique suitable to attain a high speed of a memory which is constructed in a manner such that memory cells include a field effect transistor and peripheral circuits include a bipolar transistor and a field effect transistor. According to the invention, a bipolar transistor whose collector is connected to a differential amplifier and which supplies a current to the differential amplifier in accordance with a signal which is inputted to a base or an emitter is added, and a bipolar transistor to supply a current only when writing to bit lines is connected. According to the invention, a high speed of the access time when information is read out by switching the selection bit line is accomplished. Further, the charge/discharge time of the bit line when information is written is reduced and a high speed of the writing time can be also accomplished. The improvement of the drivers of word lines and bit lines is also disclosed and a semiconductor memory which can operate at a high speed as a whole semiconductor memory can be realized.

    摘要翻译： 一种适于实现存储器的高速的电路技术，其以使得存储器单元包括场效应晶体管和外围电路的方式构造，包括双极晶体管和场效应晶体管。 根据本发明，将集电极连接到差分放大器并根据输入到基极或发射极的信号向差分放大器提供电流的双极晶体管和双极晶体管，以提供电流 只有写入位线才能连接。 根据本发明，通过切换选择位线来读取信息时的访问时间的高速度被实现。 此外，当写入信息时位线的充电/放电时间减少，并且也可以实现高速的写入时间。 还公开了字线和位线的驱动器的改进，并且可以实现可以作为整个半导体存储器以高速度操作的半导体存储器。

    Method of making semiconductor integrated circuit device
    5.
    发明授权
    Method of making semiconductor integrated circuit device 失效
    制造半导体集成电路器件的方法

    公开(公告)号：US4219369A

    公开(公告)日：1980-08-26

    申请号：US931007

    申请日：1978-08-04

    申请人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

    发明人： Katsumi Ogiue ,  Takahisa Nitta ,  Kazumichi Mitsusada ,  Masato Iwabuchi ,  Masanori Odaka

    IPC分类号： H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/388 ,  H01L21/762 ,  H01L21/8222 ,  H01L21/26

    CPC分类号： H01L21/388 ,  H01L21/033 ,  H01L21/308 ,  H01L21/32 ,  H01L21/7621 ,  H01L21/76216 ,  H01L21/76232 ,  H01L21/8222 ,  Y10S148/117 ,  Y10S148/143

    摘要： The invention relates to a method of making a semiconductor integrated circuit device, and aims at diminishing the size of the isolating region which isolates the adjacent semiconductor elements from each other. The method of the invention has the steps of forming on a substrate a deposition layer of diffused impurities of different conductivity type from that of the substrate, forming a masking film having apertures on the deposition layer, effecting an etching through making use of the masking film as the diffusion mask, so as to etch the portions of the deposition layer and the substrate under the apertures, thereby to form grooves which divide the deposition layer into island-like deposition layer sections, and stretching and diffusing the impurities in each island-like deposition layer section to form a diffusion layer which constitutes a part of a semiconductor element.

    摘要翻译： 本发明涉及一种制造半导体集成电路器件的方法，其目的在于减小将相邻半导体元件彼此隔离的隔离区的尺寸。 本发明的方法具有以下步骤：在衬底上形成不同导电类型的扩散杂质的沉积层与衬底的沉积层，在沉积层上形成具有孔的掩模膜，通过使用掩模膜进行蚀刻 作为扩散掩模，以蚀刻沉积层和基板下面的部分，从而形成将沉积层分成岛状沉积层部分的凹槽，并且将每个岛状沉积层中的杂质拉伸和扩散 沉积层部分以形成构成半导体元件的一部分的扩散层。

    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals
    6.
    发明授权
    Semiconductor integrated circuit device including input circuitry to permit operation of a Bi-CMOS memory with ECL level input signals 失效
    半导体集成电路器件包括输入电路，以允许具有ECL电平输入信号的Bi-CMOS存储器的操作

    公开(公告)号：US5457412A

    公开(公告)日：1995-10-10

    申请号：US149935

    申请日：1993-11-10

    申请人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    发明人： Nobuo Tamba ,  Masanori Odaka ,  Toshiro Hiramoto ,  Masayuki Ohayashi ,  Kayoko Saito

    IPC分类号： G11C11/413 ,  H01L21/8249 ,  H01L27/06 ,  H03K19/0175 ,  H03K19/08

    CPC分类号： H03K19/017527

    摘要： A semiconductor integrated circuit device is provided for permitting operation of a CMOS or BiCMOS memory with ECL level input signals, in which operating speed is increased and power consumption is reduced.Input signals of ECL levels are received by an input buffer for amplifying the input signals to an output signal level within a range where differential transistors of the input buffer operate in an unsaturation region. The output signal of the input buffer is supplied to a CMOS circuit or Bi-CMOS circuit which is operated by both an operating voltage having a first-stage smaller absolute value than that of the operating voltage of the input buffer and the ground potential of the circuit. This first stage CMOS or BiCMOS circuit also includes an arrangement to further amplify the received signals to provide further level conversion.Since both the input buffer and the first-stage CMOS or Bi-CMOS circuit perform signal transmission and level conversions, high-speed operation and low power consumption can be achieved by a simple structure.

    摘要翻译： 提供了一种半导体集成电路器件，用于允许具有ECL电平输入信号的CMOS或BiCMOS存储器的操作，其中操作速度增加并且功耗降低。 ECL电平的输入信号由输入缓冲器接收，用于将输入信号放大到输入缓冲器的差分晶体管在不饱和区域中操作的范围内的输出信号电平。 输入缓冲器的输出信号被提供给CMOS电路或Bi-CMOS电路，该CMOS电路或Bi-CMOS电路由具有比输入缓冲器的工作电压的绝对值小的第一级的工作电压和 电路。 该第一级CMOS或BiCMOS电路还包括进一步放大接收信号以提供进一步电平转换的装置。 由于输入缓冲器和第一级CMOS或Bi-CMOS电路都执行信号传输和电平转换，所以可以通过简单的结构实现高速操作和低功耗。

    Semiconductor memory
    7.
    发明授权
    Semiconductor memory 失效
    半导体存储器

    公开(公告)号：US4899314A

    公开(公告)日：1990-02-06

    申请号：US184661

    申请日：1988-04-21

    申请人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    发明人： Kazuhisa Miyamoto ,  Shuuichi Miyaoka ,  Masanori Odaka

    IPC分类号： G11C11/414 ,  G11C5/14

    CPC分类号： G11C5/147

    摘要： A semiconductor integrated circuit is provided having first and second level generate circuits producing different levels and first and second emitter follower circuits respectively connected thereto. A level generated by one of the first and second level generate circuits is selectively supplied to either one of the first and second emitter follower circuits. This enables the first and second emitter follower circuits to supply the respective circuits formed in a semiconductor substrate with stable reference voltages.

    摘要翻译： 提供了具有产生不同电平的第一和第二电平发生电路以及分别与其连接的第一和第二射极跟随器电路的半导体集成电路。 由第一和第二电平发生电路之一产生的电平被选择性地提供给第一和第二射极跟随器电路中的任一个。 这使得第一和第二射极跟随器电路能够在半导体衬底中形成的各个电路提供稳定的参考电压。