公开(公告)号：US4413272A

公开(公告)日：1983-11-01

申请号：US183734

申请日：1980-09-03

申请人： Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

发明人： Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

IPC分类号： G11C17/06 ,  G11C17/00 ,  G11C17/14 ,  G11C17/16 ,  H01L23/50 ,  H01L23/52 ,  H01L23/525 ,  H01L23/62

CPC分类号： G11C17/16 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002

摘要： A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

摘要翻译： 半导体存储器件具有涂覆有保护层的保险丝。 选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。 在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。 在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。

公开(公告)号：US4392211A

公开(公告)日：1983-07-05

申请号：US243927

申请日：1981-02-20

申请人： Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae ,  Hirohiko Mochizuki

发明人： Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae ,  Hirohiko Mochizuki

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/844

摘要： A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.

摘要翻译： PCT No.PCT / JP80 / 00143 Sec。 371日期：1981年2月25日 102（e）日期1981年2月20日PCT归档1980年6月24日PCT公布。 出版物WO81 / 日本1981年1月8日。一种半导体存储器件，其中并入有主存储单元矩阵的冗余存储单元阵列被公开。 主存储单元矩阵的存储单元由第一和第三解码器选择，而冗余存储单元阵列的存储单元由第二和第三解码器选择。 当由第二解码器选择冗余存储单元阵列时，通过切换电路停止向第一解码器传输时钟信号。

公开(公告)号：US4382194A

公开(公告)日：1983-05-03

申请号：US213398

申请日：1980-12-05

申请人： Masao Nakano ,  Fumio Baba ,  Hirohiko Mochizuki

发明人： Masao Nakano ,  Fumio Baba ,  Hirohiko Mochizuki

IPC分类号： H03K19/0185 ,  G11C5/14 ,  G11C11/4076 ,  G11C11/408 ,  H02M3/07 ,  H03K5/00 ,  H03K5/02 ,  H03K19/00 ,  H03K19/017 ,  H03K19/096 ,  H03K4/24 ,  H03K5/01

CPC分类号： H02M3/07 ,  G11C11/4076 ,  G11C11/4085 ,  G11C5/145 ,  H03K19/00 ,  H03K19/01707 ,  H03K19/01728 ,  H03K19/096 ,  H03K5/00

摘要： A boosting circuit boosts a voltage of a load capacitor which is charged by a specific voltage. The boosting circuit comprises a boosting capacitor one end of which is connected to receive a clock signal, a charging circuit for charging the boosting capacitor, a gate circuit provided between the load capacitor and the other end of the boosting capacitor, and a gate control circuit for opening the gate circuit upon discharging of the charge of the boosting, that is controlled by the clock signal, to the load capacitor and for closing the gate circuit during discharging of the load capacitor. The charging circuit is provided separately from a circuit for supplying the specific voltage. The charges of the boosting capacitor under the control of the clock signal flow through the gate circuit to the load capacitor.

摘要翻译： 升压电路提高由特定电压充电的负载电容器的电压。 升压电路包括一个升压电容器，其一端连接以接收时钟信号，用于对升压电容器充电的充电电路，设置在负载电容器和升压电容器的另一端之间的门电路，以及栅极控制电路 用于在由时钟信号控制的放电电荷放电到负载电容器并且在负载电容器放电期间闭合栅极电路时打开门电路。 充电电路与用于提供特定电压的电路分开设置。 在时钟信号控制下的升压电容器的电荷通过栅极电路流到负载电容器。

公开(公告)号：US4672372A

公开(公告)日：1987-06-09

申请号：US675628

申请日：1984-11-28

申请人： Hatsuo Miyahara ,  Fumio Baba ,  Hirohiko Mochizuki

发明人： Hatsuo Miyahara ,  Fumio Baba ,  Hirohiko Mochizuki

IPC分类号： H03K19/0175 ,  G11C5/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/4074 ,  H03K5/13 ,  H03K19/00 ,  H03K19/003 ,  H03K19/096 ,  H04L7/00

CPC分类号： H03K5/133 ,  G11C5/00 ,  G11C8/18

摘要： A semiconductor device having a dynamic circuit and a static circuit, wherein a clock signal, in synchronization with the operation of the static circuit, initiates the operation of the dynamic circuit. A delay circuit of a static type is provided to delay the clock signal and generate a delayed clock signal. The delayed clock signal initiates operation of one stage of the dynamic circuit. As a result, the final-operation timing of the dynamic circuit is substantially controlled by the delayed clock signal, thereby matching the operation of the dynamic circuit with the operation of the static circuit, regardless of the power supply voltage.

摘要翻译： 一种具有动态电路和静态电路的半导体器件，其中与静态电路的操作同步的时钟信号启动动态电路的操作。 提供静态延迟电路来延迟时钟信号并产生延迟的时钟信号。 延迟的时钟信号启动动态电路的一级的操作。 结果，动态电路的最终操作定时基本上被延迟的时钟信号控制，从而使动态电路的操作与静态电路的操作匹配，而与电源电压无关。

公开(公告)号：US4653027A

公开(公告)日：1987-03-24

申请号：US677580

申请日：1984-12-03

申请人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

发明人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C11/4093 ,  G11C7/00

CPC分类号： G11C7/1057 ,  G11C11/4093 ,  G11C7/1006 ,  G11C7/1051

摘要： A semiconductor memory device operated synchronously with clock signals, such as a MOS dynamic RAM device. The semiconductor memory device includes a switch circuit inserted between a prestage output amplifier circuit receiving a readout signal from a memory cell and an output buffer circuit. The switch circuit is turned on just before the output signal is supplied from the prestage output amplifier circuit to the output buffer circuit and turned off after the output condition of the output buffer circuit is settled. The potential corresponding to the output data is maintained in the circuit between the switch circuit and the output buffer circuit. The output condition of the output buffer circuit is therefore retained even during the reset period of the prestage drive circuit, and the duration period of the output signal is expanded.

摘要翻译： 与时钟信号同步操作的半导体存储器件，例如MOS动态RAM器件。 半导体存储器件包括插入在接收来自存储单元的读出信号的预置输出放大器电路与输出缓冲器电路之间的开关电路。 在将输出信号从预置输出放大器电路提供给输出缓冲器电路之前，开关电路接通，并且在输出缓冲器电路的输出状态稳定后关断。 与输出数据相对应的电位保持在开关电路和输出缓冲电路之间的电路中。 因此即使在预驱动电路的复位期间，输出缓冲电路的输出状态也被保持，并且输出信号的持续时间段被扩大。

公开(公告)号：US4680734A

公开(公告)日：1987-07-14

申请号：US762531

申请日：1985-08-05

申请人： Fumio Baba ,  Yoshihiro Takemae

发明人： Fumio Baba ,  Yoshihiro Takemae

IPC分类号： G11C11/401 ,  G11C7/00 ,  G11C7/20 ,  G11C11/40 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096

CPC分类号： G11C7/00 ,  G11C11/409 ,  G11C11/4094 ,  G11C11/4096 ,  G11C7/20

摘要： A semiconductor memory device having a data inverting circuit for selectively inverting an input/outpt data of a sense amplifier in such a way that the charging states of respective memory cells connected to two bit lines in each bit line pair become equal for the same input/output data. A clamp circuit draws the potentials of all of the bit lines to a predetermined potential in response to a clear control signal, whereby the contents of all of the memory cells are cleared at the same time.

摘要翻译： 一种半导体存储器件，具有数据反相电路，用于选择性地反相读出放大器的输入/输出数据，使得连接到每个位线对中的两个位线的各个存储单元的充电状态对于相同的输入/ 输出数据。 钳位电路响应于清除的控制信号将所有位线的电位拉到预定电位，从而同时清除所有存储单元的内容。

公开(公告)号：US4409678A

公开(公告)日：1983-10-11

申请号：US234195

申请日：1981-02-13

申请人： Yoshihiro Takemae ,  Fumio Baba

发明人： Yoshihiro Takemae ,  Fumio Baba

IPC分类号： G11C11/417 ,  G05F3/20 ,  G11C7/00 ,  G11C11/4074 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4091 ,  H01L21/822 ,  H01L27/04 ,  H03K19/003 ,  G11C7/02

CPC分类号： G11C7/00 ,  G05F3/205 ,  G11C11/4074 ,  G11C11/409 ,  G11C11/4091

摘要： Disclosed is a semiconductor memory device which comprises a sense amplifier formed on a semiconductor substrate, paired bit lines connected to the sense amplifier and memory cells connected to the bit lines wherein a predetermined bias voltage is applied to the semiconductor substrate and the reading operation is performed by amplifying by the sense amplifier a voltage difference caused between the paired bit lines due to access to the memory cells. This semiconductor memory device is characterized in that a voltage of a phase reverse to a noise transmitted to the bias voltage applied to the semiconductor substrate is applied to the semiconductor substrate through an electrostatic capacitance formed on the semiconductor substrate to cancel the noise. By virtue of this characteristic feature, influences of such noises can be eliminated in the semiconductor memory device of the present invention.

摘要翻译： 公开了一种半导体存储器件，其包括形成在半导体衬底上的读出放大器，连接到读出放大器的成对位线和连接到位线的存储器单元，其中预定的偏置电压施加到半导体衬底并进行读取操作 通过由读出放大器放大由于访问存储器单元而在成对的位线之间引起的电压差。 该半导体存储器件的特征在于，通过形成在半导体衬底上的静电电容向半导体衬底施加与施加到半导体衬底的偏置电压的噪声相反的相位电压，以消除噪声。 由于该特征，本发明的半导体存储器件中可以消除这种噪声的影响。

公开(公告)号：US4558434A

公开(公告)日：1985-12-10

申请号：US573641

申请日：1984-01-25

申请人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

发明人： Fumio Baba ,  Hirohiko Mochizuki ,  Hatsuo Miyahara

IPC分类号： B26F1/32 ,  G11C7/10 ,  G11C11/4096 ,  G11C11/40

CPC分类号： G11C11/4096 ,  G11C7/1006

摘要： A semiconductor memory device having matrix-arranged memory cells, carrying out data write or read operations to or from a selected memory cell through a pair of data buses by the selection of a word line and a pair of bit lines, includes two transfer devices which transfer data between bit lines and data buses and which are separately operated for either writing or reading. Even if a data read operation is stopped midway by a system reset or the like, the stored data in the memory cell is not destroyed.

摘要翻译： 具有矩阵排列的存储单元的半导体存储器件通过选择一条字线和一对位线，通过一对数据总线对所选存储单元执行数据写入或读操作，包括两个传输器件 在位线和数据总线之间传输数据，并分别操作写入或读取。 即使数据读取操作在系统复位等中途停止，存储单元中存储的数据也不会被破坏。

公开(公告)号：US4899310A

公开(公告)日：1990-02-06

申请号：US209819

申请日：1988-06-22

申请人： Fumio Baba ,  Kazuya Kobayashi ,  Seiji Enomoto ,  Hiroaki Ogawa

发明人： Fumio Baba ,  Kazuya Kobayashi ,  Seiji Enomoto ,  Hiroaki Ogawa

IPC分类号： G11C11/401 ,  G06F12/04 ,  G06T1/60 ,  G11C7/10

CPC分类号： G11C7/1093 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/1096

摘要： A semiconductor memory device having a register and a memory cell array includes a controlling circuit for disconnecting an input/output circuit from a data bus and turning OFF a transfer gate provided between the register and data bus in a first operation mode and for connecting the input/output circuit to the data bus and turning ON the transfer gate in a second operation mode. In the first operation mode, a data read or write operation is performed between the memory cell array and an external circuit, and alternatively in the second operation mode the data read or write operation is performed between the register and the external circuit.

公开(公告)号：US4757477A

公开(公告)日：1988-07-12

申请号：US58775

申请日：1987-06-05

申请人： Hiroshi Nagayama ,  Fumio Baba

发明人： Hiroshi Nagayama ,  Fumio Baba

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C11/4096 ,  G11C8/00

CPC分类号： G11C11/4096 ,  G11C7/1075

摘要： A dual-port semiconductor memory device having one serial memory cell of a serial access memory provided for a predetermined number of bit line pairs. A transfer gate circuit is provided between the serial memory cell and the predetermined number of bit line pairs so that only one bit line pair is selectively coupled to one serial memory at one time. Access to the dual-port semiconductor memory device is made in n/m stages when there are n bit line pairs and m serial memory cells in the serial access memory.

摘要翻译： 具有为预定数量的位线对提供的串行访问存储器的一个串行存储单元的双端口半导体存储器件。 在串行存储器单元和预定数量的位线对之间提供传输门电路，使得一次只有一个位线对选择性地耦合到一个串行存储器。 当串行存取存储器中存在n个位线对和m个串行存储单元时，可以以n / m级进行双端口半导体存储器件的访问。