公开(公告)号：US4413272A

公开(公告)日：1983-11-01

申请号：US183734

申请日：1980-09-03

申请人： Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

发明人： Hirohiko Mochizuki ,  Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae

IPC分类号： G11C17/06 ,  G11C17/00 ,  G11C17/14 ,  G11C17/16 ,  H01L23/50 ,  H01L23/52 ,  H01L23/525 ,  H01L23/62

CPC分类号： G11C17/16 ,  H01L23/5256 ,  H01L23/62 ,  H01L2924/0002

摘要： A semiconductor memory device has fuses coated with a protecting layer. The protecting layer is selectively etched to open windows so as to expose narrow center portions of the fuses. After the opening of the center windows, the fusing operation of the fuses is carried out to open a gap in the center window portion of the fuse material. In a preferred embodiment, another protective layer is then added to fill the gaps in the blown fuses.

摘要翻译： 半导体存储器件具有涂覆有保护层的保险丝。 选择性地蚀刻保护层以打开窗口，以便露出保险丝的中心部分。 在中心窗口打开之后，执行保险丝的熔合操作以在熔断体的中心窗部分中打开间隙。 在优选实施例中，然后添加另一保护层以填充熔断保险丝中的间隙。

公开(公告)号：US4392211A

公开(公告)日：1983-07-05

申请号：US243927

申请日：1981-02-20

申请人： Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae ,  Hirohiko Mochizuki

发明人： Masao Nakano ,  Fumio Baba ,  Tomio Nakano ,  Yoshihiro Takemae ,  Hirohiko Mochizuki

IPC分类号： G11C11/413 ,  G11C29/00 ,  G11C29/04 ,  G11C7/00

CPC分类号： G11C29/844

摘要： A semiconductor memory device wherein a redundancy memory cell array incorporated with main memory cell matrixes is disclosed. Memory cells of the main memory cell matrixes are selected by first and third decoders while memory cells of the redundancy memory cell array are selected by second and third decoders. When the redundancy memory cell array is selected by the second decoder, the transmission of a clock signal to the first decoders is stopped by a switching circuit.

摘要翻译： PCT No.PCT / JP80 / 00143 Sec。 371日期：1981年2月25日 102（e）日期1981年2月20日PCT归档1980年6月24日PCT公布。 出版物WO81 / 日本1981年1月8日。一种半导体存储器件，其中并入有主存储单元矩阵的冗余存储单元阵列被公开。 主存储单元矩阵的存储单元由第一和第三解码器选择，而冗余存储单元阵列的存储单元由第二和第三解码器选择。 当由第二解码器选择冗余存储单元阵列时，通过切换电路停止向第一解码器传输时钟信号。

公开(公告)号：US4601017A

公开(公告)日：1986-07-15

申请号：US561964

申请日：1983-12-15

申请人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

发明人： Hirohiko Mochizuki ,  Yoshihiro Takemae ,  Tomio Nakano ,  Kimiaki Sato

IPC分类号： G11C11/409 ,  G11C11/4094 ,  G11C11/40 ,  G11C7/00

CPC分类号： G11C11/4094

摘要： A semiconductor memory device comprises active pull-up circuits (APU.sub.1, APU.sub.2) each provided for one bit line (BL.sub.1, BL.sub.1). Each active pull-up circuit (APU.sub.1) has connections to two bit lines. That is, an active pull-up circuit (APU.sub.1) for a first bit line (BL.sub.1) comprises a first transistor (Q.sub.1) connected between a power supply terminal (V.sub.CC) and the first bit line, a second transistor (Q.sub.2) connected between the gate of the first transistor and the first bit line, and a capacitor (C.sub.1) connected to the gate of the first transistor. The gate of the second transistor is connected to a second bit line (BL.sub.1) which is paired with the first bit line. The capacitor receives an active pull-up signal (.phi..sub.AP). A circuit (Q.sub.3, Q.sub.4, Q.sub.5) is provided for transmitting a high level potential to the gate (N.sub.1) of the first transistor to precharge the capacitor.

摘要翻译： 半导体存储器件包括各自提供给一个位线（BL1，＆lt;上升和下降B1）的有源上拉电路（APU1，APU2）。 每个有源上拉电路（APU1）连接到两个位线。 也就是说，用于第一位线（BL1）的有源上拉电路（APU1）包括连接在电源端（VCC）和第一位线之间的第一晶体管（Q1），第二晶体管（Q2） 第一晶体管的栅极和第一位线，以及连接到第一晶体管的栅极的电容器（C1）。 第二晶体管的栅极连接到与第一位线配对的第二位线（＆amp;上和下）。 电容接收有源上拉信号（phi AP）。 提供电路（Q3，Q4，Q5），用于向第一晶体管的栅极（N1）发送高电平电位，以对电容器进行预充电。

公开(公告)号：US6154405A

公开(公告)日：2000-11-28

申请号：US924315

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Masao Nakano ,  Hirohiko Mochizuki ,  Hiroyoshi Tomita ,  Yasurou Matsuzaki ,  Tadao Aikawa

IPC分类号： G11C11/409 ,  G11C7/10 ,  G11C7/12 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/1048 ,  G11C7/12

摘要： A semiconductor memory device includes memory cells, word lines connected to the memory cells, bit lines connected to the memory cells, and a first circuit which resets the bit lines to a reset potential which is based on data read in a previous read cycle.

摘要翻译： 半导体存储器件包括存储器单元，连接到存储器单元的字线，连接到存储器单元的位线，以及基于在先前读取周期中读取的数据将位线复位到复位电位的第一电路。

公开(公告)号：US6028816A

公开(公告)日：2000-02-22

申请号：US924705

申请日：1997-09-05

申请人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

发明人： Yoshihiro Takemae ,  Masao Taguchi ,  Yasurou Matsuzaki ,  Hiroyoshi Tomita ,  Hirohiko Mochizuki ,  Atsushi Hatakeyama ,  Yoshinori Okajima ,  Masao Nakano

IPC分类号： G06F13/42 ,  G06F1/10 ,  G06F1/12 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/4093 ,  H03K5/00 ,  H03K5/13 ,  H03K5/135 ,  H03L7/00 ,  H03L7/081 ,  H04L7/00 ,  G11C8/00

CPC分类号： H03L7/0805 ,  G11C7/1045 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1072 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C7/222 ,  G11C7/225 ,  H03K5/133 ,  H03K5/135 ,  H03L7/00 ,  H03L7/0814 ,  G11C2207/108

摘要： A system and a semiconductor device for realizing such a system are disclosed. The system uses at least a semiconductor device for retrieving an input signal in synchronism with an internal clock generated from an external clock, the input signal remaining effectively in synchronism with the external clock. Even in the case where a phase difference develops between a clock and a signal at the receiving end, or even in the case where a phase difference develops between a clock input circuit and other signal input circuits in the semiconductor device at the receiving end, data can be transferred at high speed. Each input circuit of the semiconductor device at the receiving end includes an input timing adjusting circuit for adjusting the phase of the clock applied to the input circuit in such a manner that the input circuit retrieves the input signal in an effective and stable state. In the case where the skew between the input signals is small as compared with the skew between the input signals and the clock, an input timing adjusting circuit is shared by a plurality of the input circuits.

公开(公告)号：US4450515A

公开(公告)日：1984-05-22

申请号：US388194

申请日：1982-06-14

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Norihisa Tsuge ,  Tsuyoshi Ohira

IPC分类号： H01L27/04 ,  G05F3/20 ,  G11C11/407 ,  H01L21/822 ,  H03K17/06 ,  H03K19/00 ,  H03K19/094 ,  H02M3/18 ,  H03K3/01

CPC分类号： G05F3/205

摘要： A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

摘要翻译： 公开了一种适用于测量衬底漏电流的偏置电压发生器。 偏置电压发生器包括振荡器，由振荡器经由泵浦电容器驱动的电荷泵浦电路和电荷泵浦开关。 电荷泵开关与充电电路串联。 电荷泵开关与外部电极配合，用于控制电荷泵送电路的导通或关断状态。 通过外部电极变为浮置状态，电荷泵浦开关被切断，并且在上述测量完成并且电路从工厂出货之后用于确保电荷泵开关不可操作的电阻器。

公开(公告)号：US4752914A

公开(公告)日：1988-06-21

申请号：US739159

申请日：1985-05-30

申请人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

发明人： Masao Nakano ,  Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Kimiaki Sato ,  Norihisa Tsuge ,  Itaru Tsuge ,  Sachie Tsuge

IPC分类号： G11C29/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C29/835

摘要： A semiconductor integrated circuit including a memory unit for storing address information of a failed circuit portion and for replacing the failed circuit portion by a redundant circuit portion. The semiconductor integrated circuit provides a comparison unit for detecting coincidence between data read from the memory unit and a received input address. Data produced from the comparison by the comparison unit is delivered through an external connection terminal.

摘要翻译： 一种半导体集成电路，包括存储单元，用于存储故障电路部分的地址信息，并通过冗余电路部分来替换故障电路部分。 半导体集成电路提供用于检测从存储单元读取的数据与接收到的输入地址之间的一致性的比较单元。 通过比较单元的比较产生的数据通过外部连接终端传送。

公开(公告)号：US4707806A

公开(公告)日：1987-11-17

申请号：US712149

申请日：1985-03-15

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Takeo Tatematsu ,  Junji Ogawa ,  Takashi Horii ,  Yasuhiro Fujii ,  Masao Nakano ,  Norihisa Tsuge, deceased

IPC分类号： H01L27/00 ,  G11C8/10 ,  G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  G11C29/04 ,  H01L23/525 ,  G11C11/00

CPC分类号： G11C29/785 ,  G11C17/16 ,  G11C8/10 ,  H01L23/5256 ,  H01L2924/0002

摘要： A device connected between first and second voltage feed lines includes an information storing circuit having a fuse for storing information by blowing or not blowing the fuse, a voltage level conversion circuit connected to at least one of the first and second voltage feed lines and outputting a voltage lower than a voltage between the first and second voltage feed lines to the information storing circuit, and a circuit connected between the first and second voltage feed lines, for outputting a detection signal in response to a voltage value at the fuse in the information storing circuit to which the voltage is applied from the voltage level conversion circuit and which voltage value is varied with the blown or unblown state of the fuse.In a normal operation, the voltage output from the voltage level conversion circuit can be set as low as possible to restrain electromigration caused at the vicinity of the blown portion of the fuse to which the voltage is applied, but higher than the threshold voltage of the information detection circuit.

摘要翻译： 连接在第一和第二电压馈送线之间的装置包括信息存储电路，该信息存储电路具有熔丝，用于通过吹送或不熔断熔丝来存储信息;电压电平转换电路，连接到第一和第二电压馈送线中的至少一个并输出一个 电压低于第一和第二电压馈送线之间的电压到信息存储电路，以及电路，连接在第一和第二电压馈送线之间，用于响应于信息存储中的熔丝处的电压值输出检测信号 从电压电平转换电路向其施加电压的电路，以及哪个电压值随着保险丝的熔断或非吹出状态而变化。 在正常操作中，可以将从电压电平转换电路输出的电压设置得尽可能低以抑制在施加电压的熔丝的熔断部分附近引起的电迁移，但是高于 信息检测电路。

公开(公告)号：US4707811A

公开(公告)日：1987-11-17

申请号：US674313

申请日：1984-11-23

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

IPC分类号： G11C11/401 ,  G11C7/10 ,  G11C8/00 ,  G11C8/04 ,  G11C8/18 ,  G11C11/409

CPC分类号： G11C8/04 ,  G11C7/1024 ,  G11C7/1033 ,  G11C8/18

摘要： A semiconductor memory device has an operational mode such as a nibble mode or page mode, a first address strobe signal is kept in an active state, and a second address strobe signal is successively switched between an active state and standby state, thereby enabling successive data output. Previous output data is reset once, in accordance with the switchover of the second address strobe signal to the active state while the first address strobe signal is in the active state, before outputting data, and the reset operation for outputting is also performed when both the first and second address strobe signals are switched to the standby state, so that the period in which the data is output is expanded.

摘要翻译： 半导体存储器件具有诸如半字节模式或页面模式的操作模式，第一地址选通信号保持在活动状态，并且第二地址选通信号在活动状态和待机状态之间被连续切换，从而使能连续的数据 输出。 在输出数据之前，根据第二地址选通信号切换到激活状态的先前输出数据被复位一次，而在输出数据之前也执行用于输出的复位操作 第一和第二地址选通信号被切换到待机状态，从而扩展数据输出的周期。

公开(公告)号：US4903111A

公开(公告)日：1990-02-20

申请号：US265275

申请日：1988-10-25

申请人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

发明人： Yoshihiro Takemae ,  Tomio Nakano ,  Masao Nakano ,  Kimiaki Sato

IPC分类号： G11C17/14 ,  G11C17/16 ,  G11C29/00 ,  H01L23/525

CPC分类号： G11C29/785 ,  G11C17/16 ,  H01L23/5256 ,  H01L2924/0002

摘要： A semiconductor integrated circuit device having a fuse-blown type ROM for storing information concerning defective bits for the replacement of defective bits in a semiconductor memory device, etc., with redundant bits. The integrated circuit device comprises fuses for constituting the ROM, pads for supplying a melting current to the fuses, and PN junctions each being formed, for example, by a semiconductor substrate and a diffusion layer formed on the semiconductor substrate. Each of the fuses is melted by applying voltage to a circuit connecting the PN junction, the fuse, and the pad so that the PN junction is forward biased, thereby supplying a large current to the fuse.

摘要翻译： 一种半导体集成电路器件，具有熔丝熔断型ROM，用于存储关于半导体存储器件等中的有缺陷的位的替换的缺陷位的信息等。 集成电路装置包括用于构成ROM的保险丝，用于向保险丝提供熔化电流的焊盘，以及例如由形成在半导体衬底上的半导体衬底和扩散层形成的PN结。 通过向连接PN结，熔丝和焊盘的电路施加电压来熔化每个保险丝，使得PN结正向偏置，从而向保险丝提供大电流。