公开(公告)号：US20100102861A1

公开(公告)日：2010-04-29

申请号：US12603850

申请日：2009-10-22

申请人： Hiroki TAKAHASHI ,  Toru ISHIKAWA

发明人： Hiroki TAKAHASHI ,  Toru ISHIKAWA

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03L7/087

摘要： A DLL circuit includes a first phase comparing circuit that compares phases between an input clock signal and an output clock signal, a first delay circuit that delays the output clock signal, and a second phase comparing circuit that compares phases between the input clock signal and an output signal of the first delay circuit. A delay amount in the variable delay circuit is controlled based on a comparison result of the first phase comparing circuit and a comparison result of the second phase comparing circuit.

摘要翻译： DLL电路包括：第一相位比较电路，其比较输入时钟信号和输出时钟信号之间的相位，延迟输出时钟信号的第一延迟电路;以及第二相位比较电路，其比较输入时钟信号和 第一延迟电路的输出信号。 基于第一相位比较电路的比较结果和第二相位比较电路的比较结果来控制可变延迟电路中的延迟量。

公开(公告)号：US20120320690A1

公开(公告)日：2012-12-20

申请号：US13593018

申请日：2012-08-23

申请人： Yasushi TAKAHASHI ,  Toru ISHIKAWA

发明人： Yasushi TAKAHASHI ,  Toru ISHIKAWA

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C11/4096 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4093

摘要： A semiconductor device that includes a semiconductor substrate. First and second mode registers are provided on the semiconductor substrate and store information, respectively. First and second circuits are provided on the semiconductor substrate. The first and second circuits have substantially the same configuration. The first and second circuits perform an operation in response to the information of the first and second mode registers, respectively.

摘要翻译： 一种半导体器件，包括半导体衬底。 分别在半导体基板上提供第一和第二模式寄存器并存储信息。 第一和第二电路设置在半导体衬底上。 第一和第二电路具有基本上相同的构造。 第一和第二电路分别响应于第一和第二模式寄存器的信息执行操作。

公开(公告)号：US20080137463A1

公开(公告)日：2008-06-12

申请号：US11952633

申请日：2007-12-07

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/406 ,  G11C11/40618

摘要： A semiconductor memory device performs a refresh operation sequentially for a word line selected based on a row address when receiving a refresh request, and comprises: a memory cell array divided into M banks; a refresh counter for sequentially outputting a count value corresponding to the word line to be refreshed in response to the refresh request; and a row address converter for supplying row addresses different from one anther in at lest two banks among the M banks by converting the count value. In the semiconductor memory device, a predetermined number of selected word lines are refreshed at the same time in the banks in accordance with different patterns from one another, and the maximum value of the total number of the selected word lines refreshed at the same time for all the M banks is controlled to be lower than 2M.

摘要翻译： 半导体存储器件在接收到刷新请求时，基于行地址选择的字线顺序执行刷新操作，并且包括：划分为M个存储体的存储单元阵列; 刷新计数器，用于响应刷新请求顺序地输出与要刷新的字线对应的计数值; 以及行地址转换器，用于通过转换计数值来提供不同于M组中的至少两个存储体中的一个存储体的行地址的行地址。 在半导体存储器件中，根据彼此不同的图案，在存储体中同时刷新预定数量的所选择的字线，同时刷新所选字线的总数的最大值，用于 所有M银行都被控制在低于2M。

公开(公告)号：US20120314511A1

公开(公告)日：2012-12-13

申请号：US13491000

申请日：2012-06-07

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： G11C7/10

CPC分类号： G11C7/1057 ,  G01R31/2884 ,  G11C5/04 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

摘要翻译： 一种器件包括半导体衬底，穿透半导体衬底的第一穿透电极，第一测试焊盘和耦合在第一穿透电极和第一测试焊盘之间的第一三态缓冲器。 第一三态缓冲器在其控制端接收缓冲器控制信号。 该装置还包括向第一三态缓冲器提供缓冲器控制信号的缓冲器控制电路。

公开(公告)号：US20100271757A1

公开(公告)日：2010-10-28

申请号：US12767953

申请日：2010-04-27

申请人： Toru ISHIKAWA ,  Masayuki FUJITA ,  Takeshi SANO ,  Gaku HARADA

发明人： Toru ISHIKAWA ,  Masayuki FUJITA ,  Takeshi SANO ,  Gaku HARADA

IPC分类号： H01G9/025 ,  C08F2/46 ,  H01G9/15

CPC分类号： H01G9/15 ,  H01G9/0036 ,  H01G9/028

摘要： To provide a solid electrolytic capacitor having a high capacitance and an excellent heat resistance. A solid electrolytic capacitor includes: an anode 2; a dielectric layer 3 provided on the surface of the anode 2; a first conductive polymer layer 4a provided on the dielectric layer 3; a second conductive polymer layer 4b provided on the first conductive polymer layer 4a; a third conductive polymer layer 4c provided on the second conductive polymer layer 4b; and a cathode layer provided on the third conductive polymer layer 4c, wherein the first conductive polymer layer 4a is made of a conductive polymer film formed by polymerizing pyrrole or a derivative thereof, the second conductive polymer layer 4b is made of a conductive polymer film formed by polymerizing thiophene or a derivative thereof, and the third conductive polymer layer 4c is made of a conductive polymer film formed by electropolymerizing pyrrole or a derivative thereof.

摘要翻译： 提供具有高电容和优异耐热性的固体电解电容器。 固体电解电容器包括：阳极2; 设置在阳极2的表面上的电介质层3; 设置在电介质层3上的第一导电聚合物层4a; 设置在第一导电聚合物层4a上的第二导电聚合物层4b; 设置在第二导电聚合物层4b上的第三导电聚合物层4c; 以及设置在第三导电聚合物层4c上的阴极层，其中第一导电聚合物层4a由通过吡咯或其衍生物聚合形成的导电聚合物膜制成，第二导电聚合物层4b由形成的导电聚合物膜 通过聚合噻吩或其衍生物，并且第三导电聚合物层4c由通过电聚合吡咯或其衍生物形成的导电聚合物膜制成。

公开(公告)号：US20090140783A1

公开(公告)日：2009-06-04

申请号：US12325092

申请日：2008-11-28

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： H03H11/26

CPC分类号： H03K5/133 ,  H03K2005/00026 ,  H03K2005/00208 ,  H03L7/0814

摘要： Disclosed is a semiconductor device having a delay adjusting circuit including a delay line having N stages of differential delay circuits and N stages of differential interpolators. A differential interpolator of an Mth (where M

摘要翻译： 公开了一种具有延迟调整电路的半导体器件，该延迟调整电路包括具有N级差分延迟电路和N级差分内插器的延迟线。 Mth的差分内插器（其中M

公开(公告)号：US20140269108A1

公开(公告)日：2014-09-18

申请号：US14288428

申请日：2014-05-28

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： G11C7/10

CPC分类号： G11C7/1057 ,  G01R31/2884 ,  G11C5/04 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/48 ,  H01L22/34 ,  H01L23/481 ,  H01L2224/13025 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/15311

摘要： A device includes a semiconductor substrate, a first penetrating electrode penetrating through the semiconductor substrate, a first test pad, and a first tri-state buffer coupled between the first penetrating electrode and the first test pad. The first tri-state buffer receives a buffer control signal at a control terminal thereof. The device further includes a buffer control circuit supplying the buffer control signal to the first tri-state buffer.

摘要翻译： 一种器件包括半导体衬底，穿透半导体衬底的第一穿透电极，第一测试焊盘和耦合在第一穿透电极和第一测试焊盘之间的第一三态缓冲器。 第一三态缓冲器在其控制端接收缓冲器控制信号。 该装置还包括向第一三态缓冲器提供缓冲器控制信号的缓冲器控制电路。

公开(公告)号：US20120292759A1

公开(公告)日：2012-11-22

申请号：US13461627

申请日：2012-05-01

申请人： Toru ISHIKAWA

发明人： Toru ISHIKAWA

IPC分类号： H01L23/498

CPC分类号： H01L22/32 ,  H01L22/34 ,  H01L25/0657 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2924/15311

摘要： A device includes a semiconductor substrate, a first penetration electrode and a plurality of second penetration electrodes each penetrating the semiconductor substrate, a first terminal and a plurality of second terminals formed on a one side of the substrate, and a third terminal and a plurality of fourth terminals formed on an opposite side of the substrate. Each of the first and third terminals is vertically aligned with and electrically connected to first penetration electrode. Each of the second terminals is vertically aligned with an associated one of the second penetration electrodes and electrically connected to another one of the second penetration terminals that is not vertically aligned with the associated second terminal. Each of fourth terminals is vertically aligned with and electrically connected to an associated one of the second penetration electrodes.

摘要翻译： 一种器件包括半导体衬底，第一穿透电极和穿过半导体衬底的多个第二穿透电极，形成在衬底的一侧上的第一端子和多个第二端子，以及第三端子和多个 第四端子形成在基板的相对侧上。 第一和第三端子中的每一个与第一穿透电极垂直对准并电连接。 每个第二端子与第二穿透电极中的相关联的一个垂直对准，并且电连接到不与相关联的第二端子垂直对准的另一个第二穿透端子。 第四端子中的每一个与第二穿透电极中的相关联的一个垂直对准并电连接。

公开(公告)号：US20120187401A1

公开(公告)日：2012-07-26

申请号：US13353874

申请日：2012-01-19

申请人： Toshihiro WAKI ,  Toru ISHIKAWA

发明人： Toshihiro WAKI ,  Toru ISHIKAWA

IPC分类号： H01L23/538

CPC分类号： H01L21/565 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/481 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/92 ,  H01L24/97 ,  H01L25/03 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/05572 ,  H01L2224/06156 ,  H01L2224/06181 ,  H01L2224/13021 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/92125 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06596 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： A device includes: a first substrate including a plurality of first electrodes; a plurality of chips each including a plurality of through electrodes, the chips being stacked with each other such that the through electrodes of a lower one of the chips are connected respectively the through electrodes of an upper one of the chips to provide a chip stacked body; and a second substrate cooperating the first substrate to sandwich the chip stacked body between the first and second substrates, the second substrate including a plurality of second electrodes on a first surface that is opposite to a second surface facing the chip stacked body, each of the second electrodes being electrically connected to an associated one of the through electrodes of an uppermost one of the chips of the chip stacked body.

摘要翻译： 一种器件包括：包括多个第一电极的第一衬底; 多个芯片，每个芯片包括多个贯通电极，所述芯片彼此堆叠，使得下部芯片的贯通电极分别连接到芯片的上部芯片的贯通电极，以提供芯片堆叠体 ; 以及与所述第一基板配合以将所述芯片堆叠体夹在所述第一和第二基板之间的第二基板，所述第二基板在与面向所述芯片堆叠体的第二表面相对的第一表面上包括多个第二电极， 第二电极电连接到芯片堆叠体的最上面的一个芯片的通孔中的相关联的一个。

公开(公告)号：US20090296504A1

公开(公告)日：2009-12-03

申请号：US12260842

申请日：2008-10-29

申请人： Toru ISHIKAWA ,  Shotaro KOBAYASHI

发明人： Toru ISHIKAWA ,  Shotaro KOBAYASHI

IPC分类号： G11C29/00 ,  G11C8/18

CPC分类号： G11C29/12 ,  G11C29/1201 ,  G11C2029/5602

摘要： A semiconductor memory device may include a memory that stores data, an input/output unit and a loopback circuit. The input/output unit inputs and outputs data of a predetermined number of bits in synchronization with a clock signal. The input/output unit may include, but is not limited to, the same number of data input/output terminals as the predetermined number of bits. The loopback circuit performs loopback operation to read data of the predetermined number of bits out of a first optional area of the memory and to write the data into a second optional area of the memory.

摘要翻译： 半导体存储器件可以包括存储数据的存储器，输入/输出单元和回送电路。 输入/输出单元与时钟信号同步地输入和输出预定数量的位的数据。 输入/输出单元可以包括但不限于与预定位数相同数量的数据输入/输出端子。 环回电路执行环回操作以从存储器的第一可选区域读出预定数量的位的数据，并将数据写入存储器的第二可选区域。