公开(公告)号：US20140023695A1

公开(公告)日：2014-01-23

申请号：US13983166

申请日：2012-02-01

申请人： Yasuaki Okada ,  Katsuhiro OKada ,  Masato Nishimura ,  Yuji Kawaharada ,  Hiroo Maeda ,  Kazumitsu Yamamoto ,  Masayasu Tanaka

发明人： Yasuaki Okada ,  Katsuhiro OKada ,  Masato Nishimura ,  Yuji Kawaharada ,  Hiroo Maeda ,  Kazumitsu Yamamoto ,  Masayasu Tanaka

IPC分类号： A61K31/496 ,  A61K9/70

CPC分类号： A61K31/496 ,  A61K9/7061

摘要： A patch preparation containing a support and an adhesive layer formed on one surface of the support, wherein the adhesive layer contains 2-(4-ethyl-1-piperazinyl)-4-(4-fluorophenyl)-5,6,7,8,9,10-hexahydrocycloocta[b]pyridine or a physiologically acceptable acid addition salt thereof, an acrylic polymer, lactic acid, sesame oil and one or more kinds of stabilizers selected from 2-mercaptobenzimidazole, 2,6-di-tert-butyl-4-methylphenol and propyl gallate.A patch preparation containing a support and an adhesive layer containing lactic acid and magnesium aluminometasilicate and formed on at least one surface of the support, which preparation is superior in both skin permeability and adhesiveness in the presence of water.

摘要翻译： 一种贴剂，其包含支撑体和形成在支持体的一个表面上的粘合剂层，其中粘合剂层含有2-（4-乙基-1-哌嗪基）-4-（4-氟苯基）-5,6,7,8 ，9,10-六氢环辛[b]吡啶或其生理上可接受的酸加成盐，丙烯酸聚合物，乳酸，芝麻油和一种或多种选自2-巯基苯并咪唑，2,6-二叔丁基 -4-甲基苯酚和没食子酸丙酯。 一种贴剂，其含有载体和含有乳酸和硅酸铝镁的粘合剂层，并形成在载体的至少一个表面上，该制剂在水的存在下具有优异的皮肤渗透性和粘合性。

公开(公告)号：US20130315977A1

公开(公告)日：2013-11-28

申请号：US13983366

申请日：2012-02-01

申请人： Hiroo Maeda ,  Kazumitsu Yamamoto ,  Masayasu Tanaka

发明人： Hiroo Maeda ,  Kazumitsu Yamamoto ,  Masayasu Tanaka

IPC分类号： A61K31/496

CPC分类号： A61K31/496 ,  A61K9/7053 ,  A61K9/7061

摘要： The present invention relates to an external preparation for transdermal administration, which remarkably enhances the skin permeability of 2-(4-ethyl-1-piperazinyl)-4-(4-fluorophenyl)-5,6,7,8,9,10-hexahydrocycloocta[b]pyridine (compound A). The adhesive preparation of the present invention has an adhesive layer formed on one surface of a support, and the adhesive layer contains (i) compound A or a physiologically acceptable acid addition salt thereof, (ii) an adhesive, (iii) lactic acid, and (iv) an additive containing a particular permeation enhancer, whereby remarkably superior skin permeability is provided.

摘要翻译： 本发明涉及透皮给药的外用制剂，其显着提高了2-（4-乙基-1-哌嗪基）-4-（4-氟苯基）-5,6,7,8,9,10 - 六氢环辛[b]吡啶（化合物A）。 本发明的粘合剂制剂具有在支撑体的一个表面上形成的粘合剂层，并且粘合剂层含有（i）化合物A或其生理上可接受的酸加成盐，（ii）粘合剂，（iii）乳酸， 和（iv）含有特定渗透促进剂的添加剂，从而提供非常优异的皮肤渗透性。

公开(公告)号：US08975728B2

公开(公告)日：2015-03-10

申请号：US13612562

申请日：2012-09-12

申请人： Nobuyuki Ikarashi ,  Masayasu Tanaka

发明人： Nobuyuki Ikarashi ,  Masayasu Tanaka

IPC分类号： H01L29/20 ,  H01L21/02 ,  H01L33/00 ,  H01L33/32

CPC分类号： H01L29/32 ,  H01L21/0237 ,  H01L21/02378 ,  H01L21/02447 ,  H01L21/02458 ,  H01L21/02505 ,  H01L21/02529 ,  H01L21/0254 ,  H01L21/0262 ,  H01L21/02656 ,  H01L29/2003 ,  H01L33/007 ,  H01L33/325

摘要： A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm−2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.

摘要翻译： 在第一外延层上外延生长第二外延层。 第一外延层包括外延生长层和缺陷层。 缺陷层设置在外延生长层上并用作第一外延层的表面层。 缺陷层的缺陷密度为5×1017cm-2以上。 贯穿缺陷层的缺陷在第二外延层中形成环。

公开(公告)号：US07830703B2

公开(公告)日：2010-11-09

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： G11C11/00

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20080251849A1

公开(公告)日：2008-10-16

申请号：US10593300

申请日：2005-03-22

申请人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

发明人： Shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Atsushi Ogura ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda ,  Toru Tatsumi ,  Koji Watanabe ,  Koichi Terashima

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/6681 ,  H01L2029/7858

摘要： A semiconductor device comprising a first semiconductor region and a second semiconductor region, (a) wherein a field effect transistor is comprised of the first semiconductor region comprising at least one semiconductor layer(s) protruding upward from a substrate, a gate electrode(s) formed via an insulating film such that the gate electrode(s) strides over the semiconductor layer(s) and source/drain regions provided in the semiconductor layer(s) on both sides of the gate electrode(s), whereby a channel region is formed in at least both sides of the semiconductor layer(s), (b) wherein the second semiconductor region comprises semiconductor layers protruding upward from the substrate and placed, at least opposing the first semiconductor region at both ends in the direction perpendicular to a channel current direction and the side surface of the semiconductor layers facing the first semiconductor region is parallel to the channel current direction.

摘要翻译： 一种包括第一半导体区域和第二半导体区域的半导体器件，（a）其中场效应晶体管由包括从衬底向上突出的至少一个半导体层的第一半导体区域，栅电极， 通过绝缘膜形成，使得栅电极跨越设置在栅电极两侧的半导体层中的半导体层和源极/漏极区，由此沟道区是 形成在所述半导体层的至少两侧，（b），其中所述第二半导体区域包括从所述衬底向上突出的半导体层，并且至少相对于与沟道垂直的方向的两端处的所述第一半导体区域相对 电流方向和面对第一半导体区域的半导体层的侧表面平行于沟道电流方向。

公开(公告)号：US20080079077A1

公开(公告)日：2008-04-03

申请号：US11570037

申请日：2005-05-25

申请人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

发明人： Koichi Takeda ,  Masahiro Nomura ,  Kiyoshi Takeuchi ,  Hitoshi Wakabayashi ,  Shigeharu Yamagami ,  Risho Koh ,  Koichi Terashima ,  Katsuhiko Tanaka ,  Masayasu Tanaka

IPC分类号： H01L27/12 ,  H01L21/84

CPC分类号： H01L27/11 ,  H01L27/1104 ,  H01L27/1108 ,  H01L29/785 ,  Y10S257/903

摘要： A semiconductor device having SRAM cell units each comprising a pair of a first driving transistor and a second driving transistor, a pair of a first load transistor and a second load transistor, and a pair of a first access transistor and a second access transistor, wherein each of the transistors comprises a semiconductor layer projecting upward from a substrate plane, a gate electrode extending on opposite sides of the semiconductor layer so as to stride over a top of the semiconductor layer, a gate insulating film interposed between the gate electrode and the semiconductor layer, and a pair of source/drain areas formed in the semiconductor layer; and the first and second driving transistors each have a channel width larger than that of at least either each of the load transistors or each of the access transistors.

摘要翻译： 一种具有SRAM单元单元的半导体器件，每个SRAM单元包括一对第一驱动晶体管和第二驱动晶体管，一对第一负载晶体管和第二负载晶体管，以及一对第一存取晶体管和第二存取晶体管，其中 每个晶体管包括从衬底平面向上突出的半导体层，在半导体层的相对侧上延伸以跨越半导体层的顶部的栅极电极，插入在栅极电极和半导体之间的栅极绝缘膜 层，以及形成在半导体层中的一对源极/漏极区域; 并且第一和第二驱动晶体管的沟道宽度均大于至少任一个负载晶体管或每个存取晶体管的沟道宽度。

公开(公告)号：US20070075372A1

公开(公告)日：2007-04-05

申请号：US10576412

申请日：2004-10-19

申请人： Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

发明人： Koichi Terashima ,  Kiyoshi Takeuchi ,  shigeharu Yamagami ,  Hitoshi Wakabayashi ,  Atsushi Ogura ,  Koji Watanabe ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka

IPC分类号： H01L23/62

CPC分类号： H01L29/7853 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a semiconductor device wherein at least the largest width of a source/drain region is larger than the width of a semiconductor region and the source/drain region has a slope having a width continuously increasing from the uppermost side to the substrate side, and a silicide film is formed in the surface of the slope.

摘要翻译： 提供了一种半导体器件，其中源极/漏极区域的至少最大宽度大于半导体区域的宽度，并且源极/漏极区域具有从最上侧到衬底侧的宽度连续增加的斜率， 并且在斜面的表面中形成硅化物膜。

公开(公告)号：US20090014795A1

公开(公告)日：2009-01-15

申请号：US11658564

申请日：2005-07-14

申请人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

发明人： Risho Koh ,  Katsuhiko Tanaka ,  Shigeharu Yamagami ,  Koichi Terashima ,  Hitoshi Wakabayashi ,  Kiyoshi Takeuchi ,  Masayasu Tanaka ,  Masahiro Nomura ,  Koichi Takeda

IPC分类号： H01L29/786 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/785 ,  H01L29/66795

摘要： A π gate FinFET structure having reduced variations in off-current and parasitic capacitance and a method for production thereof are provided. The structure of an element is improved so that an off-current suppressing capability can be exhibited more strongly. A field effect transistor, wherein a first insulating film and a semiconductor region are provided so as to protrude upward with respect to the flat surface of a base, the field effect transistor has a gate electrode, a gate insulating film and a source/drain region, and a channel is formed at least on the side surface of the semiconductor region, wherein that the first insulating film is provided on an etch stopper layer composed of a material having an etching rate lower than at least the lowermost layer of the first insulating film for etching under a predetermined condition.

摘要翻译： 提供了一种具有减小的截止电流和寄生电容的变化的p型门FinFET结构及其制造方法。 改善了元件的结构，使得能够更强烈地显示出截止电流的能力。 一种场效应晶体管，其中第一绝缘膜和半导体区域设置成相对于基底的平坦表面向上突出，所述场效应晶体管具有栅极电极，栅极绝缘膜和源极/漏极区域 并且至少在所述半导体区域的侧表面上形成沟道，其中所述第一绝缘膜设置在由蚀刻速率低于所述第一绝缘膜的最下层的蚀刻速率的材料构成的蚀刻停止层上 用于在预定条件下蚀刻。

公开(公告)号：US20070187682A1

公开(公告)日：2007-08-16

申请号：US10569451

申请日：2004-08-27

申请人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

发明人： Kiyoshi Takeuchi ,  Koji Watanabe ,  Koichi Terashima ,  Atsushi Ogura ,  Toru Tatsumi ,  Koichi Takeda ,  Masahiro Nomura ,  Masayasu Tanaka ,  Shigeharu Yamagami ,  Hitoshi Wakabayashi

IPC分类号： H01L29/04

CPC分类号： H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/82385 ,  H01L27/092 ,  H01L27/0924 ,  H01L29/045 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/7854

摘要： There is provided a semiconductor device comprising an n-type and a p-type field effect transistors, meeting the conditions that in terms of a crystal orientation of the protruding semiconductor region constituting the n-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {100} plane substantially orthogonal to the {100} plane, and that in terms of a crystal orientation of the protruding semiconductor region constituting the p-type field effect transistor, its plane parallel to the substrate is substantially a {100} plane and its side surface is a {110} plane substantially orthogonal to the {100} plane.

摘要翻译： 提供一种包括n型和p型场效应晶体管的半导体器件，满足以下条件：就组成n型场效应晶体管的突出半导体区域的晶体取向而言，其平行于衬底的平面 基本上是{100}面，其侧面是与{100}面大致正交的{100}面，就构成p型场效应晶体管的突出半导体区域的晶体取向而言，其平面 与基板平行的基本上是{100}平面，其侧面是与{100}平面基本正交的{110}平面。

公开(公告)号：US5694021A

公开(公告)日：1997-12-02

申请号：US395504

申请日：1995-02-27

申请人： Shizuo Morioka ,  Nobuyuki Hosoya ,  Yoshiaki Ukiya ,  Katsuo Ozawa ,  Masayasu Tanaka

发明人： Shizuo Morioka ,  Nobuyuki Hosoya ,  Yoshiaki Ukiya ,  Katsuo Ozawa ,  Masayasu Tanaka

IPC分类号： G01R31/36 ,  H01M10/0525 ,  H01M10/42 ,  H01M10/44 ,  H02J7/00

CPC分类号： G01R31/3624 ,  G01R31/3648 ,  H01M10/4257 ,  H01M10/44 ,  H02J7/0073 ,  H02J7/0085 ,  H01M10/0525

摘要： A system comprises a rechargeable battery charged with a constant voltage and a charger. The battery includes a storage unit storing charge voltage data. The charger reads the charge voltage data from the storage unit and charges the battery in accordance with the read charge voltage data. In one aspect, the charger is assigned identification data to identify the charger and charge the battery. In another aspect, a charge controller includes a full-charge detecting means for detecting that the battery is fully charged based upon current measured from the battery.

摘要翻译： 一种系统包括充有恒定电压的充电电池和充电器。 电池包括存储充电电压数据的存储单元。 充电器从存储单元读取充电电压数据，并根据读取的充电电压数据对电池充电。 在一个方面，充电器被分配识别数据以识别充电器并对电池充电。 另一方面，充电控制器包括：充电检测装置，用于根据从电池测得的电流来检测电池是否充满电。