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公开(公告)号：US20060205106A1
公开(公告)日：2006-09-14
申请号：US11208740
申请日：2005-08-23
IPC分类号： H01L21/00
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2201/0264 , B81C2203/0714 , B81C2203/0742
摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.
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2.发明授权公开(公告)号：US08129802B2
公开(公告)日：2012-03-06
申请号：US12216359
申请日：2008-07-02
IPC分类号： H01L29/84
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2201/0264 , B81C2203/0714 , B81C2203/0742
摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.
摘要翻译： 在半导体集成电路（CMOS等）和微机器单片集成在半导体基板上的集成MEMS的制造技术中，能够制造集成MEMS而不使用与正常制造不同的特殊工艺的技术 提供了半导体集成电路的技术。 通过使用CMOS集成电路工艺与集成电路一起形成MEMS结构。 例如，当形成加速度传感器时，通过使用CMOS互连技术形成由可移动质量块，弹性梁和固定梁构成的结构。 此后，通过使用CMOS工艺蚀刻层间电介质等以形成空腔。 然后，用电介质密封蚀刻中使用的细孔。
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3.发明申请公开(公告)号：US20090064785A1
公开(公告)日：2009-03-12
申请号：US12216359
申请日：2008-07-02
IPC分类号： G01P15/125
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2201/0264 , B81C2203/0714 , B81C2203/0742
摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.
摘要翻译： 在半导体集成电路（CMOS等）和微机器单片集成在半导体基板上的集成MEMS的制造技术中，能够制造集成MEMS而不使用与正常制造不同的特殊工艺的技术 提供了半导体集成电路的技术。 通过使用CMOS集成电路工艺与集成电路一起形成MEMS结构。 例如，当形成加速度传感器时，通过使用CMOS互连技术形成由可移动质量块，弹性梁和固定梁构成的结构。 此后，通过使用CMOS工艺蚀刻层间电介质等以形成空腔。 然后，用电介质密封蚀刻中使用的细孔。
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4.发明授权公开(公告)号：US07402449B2
公开(公告)日：2008-07-22
申请号：US11208740
申请日：2005-08-23
IPC分类号： H01L21/00
CPC分类号： B81C1/00246 , B81B2201/0235 , B81B2201/0264 , B81C2203/0714 , B81C2203/0742
摘要： In the manufacturing technology of an integrated MEMS in which a semiconductor integrated circuit (CMOS or the like) and a micro machine are monolithically integrated on a semiconductor substrate, a technology capable of manufacturing the integrated MEMS without using a special process different from the normal manufacturing technology of a semiconductor integrated circuit is provided. A MEMS structure is formed together with an integrated circuit by using the CMOS integrated circuit process. For example, when forming an acceleration sensor, a structure composed of a movable mass, an elastic beam and a fixed beam is formed by using the CMOS interconnect technology. Thereafter, an interlayer dielectric and the like are etched by using the CMOS process to form a cavity. Then, fine holes used in the etching are sealed with a dielectric.
摘要翻译： 在半导体集成电路（CMOS等）和微机器单片集成在半导体基板上的集成MEMS的制造技术中，能够制造集成MEMS而不使用与正常制造不同的特殊工艺的技术 提供了半导体集成电路的技术。 通过使用CMOS集成电路工艺与集成电路一起形成MEMS结构。 例如，当形成加速度传感器时，通过使用CMOS互连技术形成由可移动质量块，弹性梁和固定梁构成的结构。 此后，通过使用CMOS工艺蚀刻层间电介质等以形成空腔。 然后，用电介质密封蚀刻中使用的细孔。
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公开(公告)号：US07325457B2
公开(公告)日：2008-02-05
申请号：US11492961
申请日：2006-07-26
IPC分类号： G01L9/12
CPC分类号： G01L9/0073 , B60C23/0408 , G01D5/2417 , G01L9/12 , G01L27/007
摘要： A sensor and sensor module with small power consumption and high reliability are disclosed. The sensor includes a capacitor having a capacitance varying with a physical quantity, a capacitance-voltage conversion circuit for converting the capacitance of the capacitor into a voltage, and a control signal generation circuit for generating a plurality of control signals. The capacitor has a frequency-capacitance characteristic with a resonant frequency. In a measurement of the physical quantity, the capacitance of the capacitor is measured with one of the control signals having a first frequency which is much higher or much lower than the resonant frequency. In a self-diagnosis of the sensor, the capacitance of the capacitor is measured with another one of the control signals having a second frequency which is equal or close to the resonant frequency.
摘要翻译： 公开了具有小功耗和高可靠性的传感器和传感器模块。 传感器包括具有物理量变化的电容的电容器，用于将电容器的电容转换为电压的电容 - 电压转换电路，以及用于产生多个控制信号的控制信号产生电路。 电容器具有谐振频率的频率 - 电容特性。 在物理量的测量中，电容器的电容被测量，其中一个控制信号具有比谐振频率高得多或低得多的第一频率。 在传感器的自诊断中，电容器的电容用另一个控制信号测量，其中第二频率等于或接近谐振频率。
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公开(公告)号：US20070068266A1
公开(公告)日：2007-03-29
申请号：US11492961
申请日：2006-07-26
IPC分类号： G01L9/12
CPC分类号： G01L9/0073 , B60C23/0408 , G01D5/2417 , G01L9/12 , G01L27/007
摘要： A sensor and sensor module with small power consumption and high reliability are disclosed. The sensor includes a capacitor having a capacitance varying with a physical quantity, a capacitance-voltage conversion circuit for converting the capacitance of the capacitor into a voltage, and a control signal generation circuit for generating a plurality of control signals. The capacitor has a frequency-capacitance characteristic with a resonant frequency. In a measurement of the physical quantity, the capacitance of the capacitor is measured with one of the control signals having a first frequency which is much higher or much lower than the resonant frequency. In a self-diagnosis of the sensor, the capacitance of the capacitor is measured with another one of the control signals having a second frequency which is equal or close to the resonant frequency.
摘要翻译： 公开了具有小功耗和高可靠性的传感器和传感器模块。 传感器包括具有物理量变化的电容的电容器，用于将电容器的电容转换为电压的电容 - 电压转换电路，以及用于产生多个控制信号的控制信号产生电路。 电容器具有谐振频率的频率 - 电容特性。 在物理量的测量中，电容器的电容被测量，其中一个控制信号具有比谐振频率高得多或低得多的第一频率。 在传感器的自诊断中，电容器的电容用另一个控制信号测量，其中第二频率等于或接近谐振频率。
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7.发明授权Semiconductor device with large blocking voltage and method of manufacturing the same 有权具有大阻断电压的半导体器件及其制造方法公开(公告)号：US07772613B2
公开(公告)日：2010-08-10
申请号：US12533740
申请日：2009-07-31
申请人： Haruka Shimizu , Natsuki Yokoyama
发明人： Haruka Shimizu , Natsuki Yokoyama
IPC分类号： H01L29/80
CPC分类号： H01L29/0619 , H01L29/0661 , H01L29/1066 , H01L29/1608 , H01L29/66068 , H01L29/66909 , H01L29/8083
摘要： A normally-off type junction FET in which a channel resistance is reduced without lowering its blocking voltage is provided. In a junction FET formed with using a substrate made of silicon carbide, an impurity concentration of a channel region (second epitaxial layer) is made higher than an impurity concentration of a first epitaxial layer to be a drift layer. The channel region is formed of a first region in which a channel width is constant and a second region below the first region in which the channel width becomes wider toward the drain (substrate) side. A boundary between the first epitaxial layer and the second epitaxial layer is positioned in the second region in which the channel width becomes wider toward the drain (substrate) side.
摘要翻译： 提供了其中通道电阻降低而不降低其阻断电压的常闭型结型FET。 在使用由碳化硅制成的衬底形成的结型FET中，使沟道区（第二外延层）的杂质浓度高于作为漂移层的第一外延层的杂质浓度。 沟道区域由沟道宽度恒定的第一区域和沟道宽度朝向漏极（衬底）侧变宽的第一区域下方的第二区域形成。 第一外延层和第二外延层之间的边界位于沟道宽度朝向漏极（基板）侧变宽的第二区域中。
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公开(公告)号：US20100163935A1
公开(公告)日：2010-07-01
申请号：US12639054
申请日：2009-12-16
申请人： Haruka Shimizu , Natsuki Yokoyama
发明人： Haruka Shimizu , Natsuki Yokoyama
IPC分类号： H01L29/808
CPC分类号： H01L29/8083 , H01L29/42316 , H01L29/66068 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H01L2924/00014 , H01L2924/00
摘要： In a junction FET of a normally-off type, a technique capable of achieving both of improvement of a blocking voltage and reduction of an ON resistance is provided. In a junction FET using silicon carbide as a substrate material, impurities are doped to a vicinity of a p-n junction between a gate region and a channel-formed region, the impurities having a conductive type which is reverse to that of impurities doped in the gate region and same as that of impurities doped in the channel-formed region. In this manner, an impurity profile of the p-n junction becomes abrupt, and further, an impurity concentration of a junction region forming the p-n junction with the gate region in the channel-formed region is higher than those of a center region in the channel-formed region and of an epitaxial layer.
摘要翻译： 在常闭型的结型FET中，提供了能够实现阻断电压的提高和导通电阻的降低的技术。 在使用碳化硅作为衬底材料的接合FET中，杂质被掺杂到栅极区域和沟道形成区域之间的pn结附近，杂质具有与掺杂在栅极中的杂质相反的导电类型 区域和与在沟道形成区域中掺杂的杂质相同。 以这种方式，pn结的杂质分布变得突然，并且形成与沟道形成区域中的栅极区域的pn结的结区域的杂质浓度高于沟道形成区域中的中心区域的杂质浓度， 形成区域和外延层。
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公开(公告)号：US07310563B2
公开(公告)日：2007-12-18
申请号：US11320778
申请日：2005-12-30
申请人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
发明人： Natsuki Yokoyama , Yoshifumi Kawamoto , Eiichi Murakami , Fumihiko Uchida , Kenichi Mizuishi , Yoshio Kawamura
IPC分类号： G06F19/00
CPC分类号： C23C14/568 , C23C16/54 , G05B19/41865 , G05B2219/45031 , H01L21/67161 , H01L21/67167 , H01L21/67173 , H01L21/67184 , H01L21/67276 , H01L21/67727 , H01L21/67745 , Y02P90/14 , Y02P90/20 , Y02P90/28 , Y10S414/135 , Y10S414/137 , Y10S438/908 , Y10T29/41
摘要： A fabricating method for a system including a plurality of processing apparatuses connected to each other by an inter-apparatus transporter. The semiconductor waters are processed in the processing apparatuses and are transported to specified processing apparatuses in different time interval that are set to N times a unit time interval. Since the fabricating system includes processing apparatuses and an inter-apparatus transporter that are periodically controlled at time intervals related to a unit time, intervals related to a unit time, the scheduling of a plurality of works can be made efficiently to enhance the level of optimization, thus improving the productivity.
摘要翻译： 一种用于系统的制造方法，包括通过机构间运送器彼此连接的多个处理装置。 半导体水在处理装置中进行处理，并以不同的时间间隔被传送到规定的处理装置，时间间隔设定为单位时间间隔的N倍。 由于制造系统包括以与单位时间相关的时间间隔周期性地控制的处理装置和装置间运输装置，所以与单位时间相关的间隔，可以有效地进行多个作业的调度以增强优化水平 ，从而提高生产率。
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10.发明授权公开(公告)号：US07115943B2
公开(公告)日：2006-10-03
申请号：US11013406
申请日：2004-12-17
申请人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
发明人： Toshiyuki Mine , Natsuki Yokoyama , Kan Yasui
IPC分类号： H01L29/792
CPC分类号： H01L21/28282 , H01L27/11568 , H01L29/792
摘要： A MONOS nonvolatile memory of a split gate structure, wherein writing and erasing are performed by hot electrons and hot holes respectively, is prone to cause electrons not to be erased and to remain in an Si nitride film on a select gate electrode sidewall and that results in the deterioration of rewriting durability. When long time erasing is applied as a measure to solve the problem, drawbacks appear, such as the increase of a circuit area caused by the increase of the erasing current and the deterioration of retention characteristics. In the present invention, an Si nitride film is formed by the reactive plasma sputter deposition method that enables oriented deposition and the Si nitride film on a select gate electrode sidewall is removed at the time when a top Si oxide film is formed.
摘要翻译： 分离栅结构的MONOS非易失性存储器，其中由热电子和热孔分别执行写入和擦除容易导致电子不被擦除并且保留在选择栅极电极侧壁上的氮化硅膜中，并且结果 在改写耐久性的恶化。 当长时间擦除作为解决该问题的措施时，会出现缺点，例如由擦除电流的增加引起的电路面积的增加和保留特性的劣化。 在本发明中，通过能够进行取向沉积的反应等离子体溅射沉积方法形成氮化硅膜，并且在形成顶部Si氧化物膜时，在选择栅电极侧壁上除去Si氮化物膜。
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