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73 条记录 (耗时 0.025 秒)

    Folding type A/D converter and folding type A/D converter circuit
    1.
    发明授权
    Folding type A/D converter and folding type A/D converter circuit 有权
    折叠式A / D转换器和折叠式A / D转换电路

    公开(公告)号：US06069579A

    公开(公告)日：2000-05-30

    申请号：US131238

    申请日：1998-08-07

    申请人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

    发明人： Masao Ito ,  Takeshi Shigenobu ,  Toshio Kumamoto ,  Takahiro Miki ,  Hiroshi Komurasaki

    IPC分类号： H03M1/14 ,  H03M1/20 ,  H03M1/36 ,  H03M1/12

    CPC分类号： H03M1/205 ,  H03M1/141

    摘要： An A/D converter simplifies its circuit configuration without deteriorating accuracy in A/D conversion. A circuit is formed of a folding and interpolation type. A gain-variable pre-amplifier group 11 amplifies each of reference voltages Vref1 to VrefN and an analog input voltage Vin, to output the result to a folding amplifier group 12, while a gain-variable pre-amplifier group 21 amplifies each of reference voltages Vrr1 to VrrJ and the analog input voltage Vin, to output the result to a comparator group 24. Each of pre-amplifiers constituting the gain-variable pre-amplifier groups 11 and 21 has an amplification factor that varies in upper and lower comparison periods according to a clock control signal .PHI.cnt.

    摘要翻译： A / D转换器简化了其电路配置，而不会降低A / D转换的精度。 电路由折叠和内插形式组成。 增益可变前置放大器组11放大每个参考电压Vref1至VrefN和模拟输入电压Vin，以将结果输出到折叠放大器组12，而增益可变的前置放大器组21放大每个参考电压 Vrr1至VrrJ和模拟输入电压Vin，将结果输出到比较器组24.构成增益可变前置放大器组11和21的每个前置放大器具有在上和下比较周期内变化的放大系数， 到时钟控制信号PHI cnt。

    Sample hold circuit having a switch
    2.
    发明授权
    Sample hold circuit having a switch 失效
    具有开关的采样保持电路

    公开(公告)号：US06232804B1

    公开(公告)日：2001-05-15

    申请号：US09413751

    申请日：1999-10-06

    申请人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

    发明人： Takeshi Shigenobu ,  Masao Ito ,  Toshio Kumamoto

    IPC分类号： G11C2702

    CPC分类号： G11C27/026

    摘要： In a sample hold circuit (6, 50, 60) capable of relaxing a dependency of a voltage of an analogue input signal on an ON resistance of a switch (2). In the sample hold circuit (6, 50, 60), plural reference voltages VrefN are supplied, and unit switches (11e) forming the switch (2) are selectively activated (an ON state) based on a comparison results (whether or not the voltage of the analogue input signal is greater than each reference voltage) from plural comparison circuits (13e) whose operations are performed based on the voltage of the analogue input signal (1).

    摘要翻译： 在能够放松模拟输入信号的电压对开关（2）的导通电阻的依赖性的采样保持电路（6,50,60）中。 在采样保持电路（6,50,60）中，提供多个参考电压VrefN，并且基于比较结果（形成开关（2））的单元开关（11e）是否被选择性地激活（ON状态） 根据模拟输入信号（1）的电压执行其操作的多个比较电路（13e），模拟输入信号的电压大于每个参考电压）。

    D/A and A/D converters
    3.
    发明授权
    D/A and A/D converters 失效
    D / A和A / D转换器

    公开(公告)号：US5995031A

    公开(公告)日：1999-11-30

    申请号：US968207

    申请日：1997-11-12

    申请人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

    发明人： Takashi Okuda ,  Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki

    IPC分类号： H03M1/10 ,  H03M1/06 ,  H03M1/74 ,  H03M1/66

    CPC分类号： H03M1/0663 ,  H03M1/747 ,  H03M3/464 ,  H03M3/502

    摘要： A multi-bit D/A converter which improves the linearity of an analog output relative to a digital input is provided. A switch control circuit (1) turns on D some of a plurality of switches (S1 to SM) which are arranged in ascending order starting with a switch determined by a start position determination circuit (3) and turns off the remaining switches, the number of switches turned on being dependent on a digital signal (DIG). The start position determination circuit (3) sequentially changes the switches (S1, S3, S5, . . . ) serving as a selection start position to determine the selection start position for each input of the digital signal (DIG) provided in synchronism with a clock signal (CLK).

    摘要翻译： 提供了一种提高模拟输出相对于数字输入的线性度的多位D / A转换器。 开关控制电路（1）接通D开始的开关位置确定电路（3）确定的开关的升序排列的多个开关（S1至SM）中的一些，并且关闭其余的开关 开关依赖于数字信号（DIG）。 开始位置确定电路（3）顺序地改变用作选择开始位置的开关（S1，S3，S5 ...），以确定与设置的与数字信号（DIG）同步的数字信号（DIG）的每个输入的选择开始位置 时钟信号（CLK）。

    Pipeline type analog to digital converter including plural series connected analog to digital converter stages
    4.
    发明授权
    Pipeline type analog to digital converter including plural series connected analog to digital converter stages 失效
    管道式模数转换器包括多个串联的模数转换器级

    公开(公告)号：US5629700A

    公开(公告)日：1997-05-13

    申请号：US552016

    申请日：1995-11-02

    申请人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

    发明人： Toshio Kumamoto ,  Osamu Matsumoto ,  Takahiro Miki ,  Masao Ito ,  Takashi Okuda

    IPC分类号： H03M1/14 ,  H03M1/00 ,  H03M1/06 ,  H03M1/12 ,  H03M1/16 ,  H03M1/44 ,  H03M1/34

    CPC分类号： H03M1/002 ,  H03M1/0682 ,  H03M1/069 ,  H03M1/1215 ,  H03M1/167

    摘要： An A/D converter block A/D1 converts an analog input signal Vin to a digital signal and outputs its D/A output. First SH/SUBT7, 8 sample the signal Vin and a voltage VRM at the same timing with said A/D conversion and output the results of subtraction of the respective sampling values and the D/A output during holding, respectively. The both results of subtraction are several tens mV and there is no need of taking account of the linearity of a differential amplifier DIFF11. During the sampling, a circuit SHR1 outputs the differential voltages between each reference tap voltage taken out from specific 2 points of the ladder-type resistor in the A/D converter block A/D1 and the voltage VRM while a differential amplifier DIFF12 applies the reference voltages to the next A/D converter block A/D2. Such operations are performed in each stage. Thus, it becomes possible to make any S/H circuit and amplifier of excellent linearity in the first stage unnecessary to reduce the electric power consumption.

    摘要翻译： A / D转换器模块A / D1将模拟输入信号Vin转换为数字信号并输出​​其D / A输出。 第一SH / SUBT7,8以与所述A / D转换相同的定时采样信号Vin和电压VRM，并分别输出相应采样值和保持期间的D / A输出的结果。 减法的结果都是几十mV，不需要考虑差分放大器DIFF11的线性度。 在采样期间，电路SHR1输出从A / D转换器模块A / D1中的梯形电阻器的特定2点取出的每个参考分接电压与电压VRM之间的差分电压，而差分放大器DIFF12施加参考 电压到下一个A / D转换器模块A / D2。 这样的操作在每个阶段进行。 因此，可以使得在第一级中具有优异线性度的任何S / H电路和放大器不必减少电力消耗。

    Voltage comparator and A/D converter
    5.
    发明授权
    Voltage comparator and A/D converter 失效
    电压比较器和A / D转换器

    公开(公告)号：US5936434A

    公开(公告)日：1999-08-10

    申请号：US912813

    申请日：1997-08-19

    申请人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

    发明人： Toshio Kumamoto ,  Masao Ito ,  Takahiro Miki ,  Takashi Okuda

    IPC分类号： H03M1/34 ,  H03F3/45 ,  H03K5/08 ,  H03K5/24 ,  H03K5/153

    CPC分类号： H03K5/249 ,  H03K5/2481

    摘要： An object is to obtain a voltage comparator capable of high-accuracy voltage comparison. An input voltage (VIN) and a reference voltage (VREF) are connected to one electrode of a capacitor (C1) through switches (S1) and (S2), respectively. The other electrode of the capacitor (C1) is connected to the input portion of an inverter (INV1). The output portion of the inverter (INV1) is connected to the input portion of an inverter (INV3) and is also fed back to the input through a switch (S3). An inverter (INV11) is further connected in parallel with the inverter (INV1), wherein the input/output characteristics of the inverters (INV1, INV3 and INV11) are set equal.

    摘要翻译： 目的是获得能够进行高精度电压比较的电压比较器。 分别通过开关（S1）和（S2）将输入电压（VIN）和参考电压（VREF）连接到电容器（C1）的一个电极。 电容器（C1）的另一个电极连接到逆变器（INV1）的输入部分。 逆变器（INV1）的输出部分连接到逆变器（INV3）的输入部分，并通过开关（S3）反馈到输入端。 反相器（INV11）进一步与反相器（INV1）并联连接，其中反相器（INV1，INV3和INV11）的输入/输出特性被设定为相等。

    Digital-to-analog converter
    10.
    发明授权
    Digital-to-analog converter 失效
    数模转换器

    公开(公告)号：US06703957B2

    公开(公告)日：2004-03-09

    申请号：US10143878

    申请日：2002-05-14

    申请人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

    发明人： Yasuo Morimoto ,  Toshio Kumamoto ,  Takashi Okuda ,  Takahiro Miki

    IPC分类号： H03M166

    CPC分类号： H03M1/0614 ,  H03K5/01 ,  H03K5/133 ,  H03M1/822 ,  H03M3/372 ,  H03M3/506

    摘要： When forming PDM pulses by a D/A converter in accordance with digital signals, the D/A converter causes at least one of the rising stage and the falling stage of each of the PDM pulses to change stepwise. In addition, when forming PWM pulses by another D/A converter, the D/A converter causes at least one of the rising stage and the falling stage of each of the PWM pulses to change stepwise.

    摘要翻译： 当通过D / A转换器根据数字信号形成PDM脉冲时，D / A转换器使得每个PDM脉冲的上升沿和下降沿中的至少一个逐步改变。 此外，当由另一个D / A转换器形成PWM脉冲时，D / A转换器使每个PWM脉冲的上升沿和下降沿中的至少一个逐步改变。