公开(公告)号：US10764495B2

公开(公告)日：2020-09-01

申请号：US16217536

申请日：2018-12-12

申请人： Hiroyasu Uehara ,  Masakazu Terauchi ,  Masashi Miyata ,  Hiroshi Kano ,  Akira Nakano ,  Takeyoshi Nishimura

发明人： Hiroyasu Uehara ,  Masakazu Terauchi ,  Masashi Miyata ,  Hiroshi Kano ,  Akira Nakano ,  Takeyoshi Nishimura

IPC分类号： H04N5/262 ,  H04N5/232 ,  H04N5/347 ,  H04N5/349

摘要： An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

公开(公告)号：US20190191082A1

公开(公告)日：2019-06-20

申请号：US16217536

申请日：2018-12-12

申请人： Hiroyasu Uehara ,  Masakazu Terauchi ,  Masashi Miyata ,  Hiroshi Kano ,  Akira Nakano ,  Takeyoshi Nishimura

发明人： Hiroyasu Uehara ,  Masakazu Terauchi ,  Masashi Miyata ,  Hiroshi Kano ,  Akira Nakano ,  Takeyoshi Nishimura

IPC分类号： H04N5/232 ,  H04N5/262 ,  H04N5/347

摘要： An image processing apparatus includes processing circuitry. The processing circuitry is configured to detect a positional shift amount of each of a plurality of images; select a composite target image from the plurality of images based on the detected positional shift amount; and obtain a composite image based on the positional shift amount and the selected composite target image.

公开(公告)号：US11012633B2

公开(公告)日：2021-05-18

申请号：US16358923

申请日：2019-03-20

申请人： Masakazu Terauchi ,  Hiroyasu Uehara ,  Masashi Miyata ,  Hiroshi Kano ,  Takeyoshi Nishimura

发明人： Masakazu Terauchi ,  Hiroyasu Uehara ,  Masashi Miyata ,  Hiroshi Kano ,  Takeyoshi Nishimura

IPC分类号： H04N5/235 ,  H04N5/349 ,  H04N5/232 ,  H04N5/367

摘要： An image capturing apparatus includes an image data acquirer configured to acquire pieces of image data at a plurality of relative movement positions to which an imaging surface of an imaging sensor is relatively moved with respect to an object light flux; an exposure changer configured to change an exposure when acquiring the pieces of image data at the plurality of relative movement positions; a dynamic range adjuster configured to adjust a dynamic range of the acquired pieces of image data; and an image data combiner configured to obtain composite image data of the pieces of image data, based on a positional shift amount between the pieces of image data and the dynamic range.

公开(公告)号：US09553185B2

公开(公告)日：2017-01-24

申请号：US13634603

申请日：2010-05-27

申请人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

发明人： Kin-On Sin ,  Chun-Wai Ng ,  Hitoshi Sumida ,  Yoshiaki Toyada ,  Akihiko Ohi ,  Hiroyuki Tanaka ,  Takeyoshi Nishimura

IPC分类号： H01L29/66 ,  H01L29/78 ,  H01L29/423 ,  H01L21/265 ,  H01L29/08

CPC分类号： H01L29/66734 ,  H01L21/26586 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/4236 ,  H01L29/7813

摘要： A mask used to form an n+ source layer (11) is formed by a nitride film on the surface of a substrate before a trench (7) is formed. At this time, a sufficient width of the n+ source layer (11) on the surface of the substrate is secured. Thereby, stable contact between the n+ source layer (11) and a source electrode (15) is obtained. A CVD oxide film (12) that is an interlayer insulating film having a thickness of 0.1 micrometer or more and 0.3 micrometer or less is formed on doped poly-silicon to be used as a gate electrode (10a) embedded in the trench (7), and non-doped poly-silicon (13) that is not oxidized is formed on the CVD oxide film (12). Thereby, generation of void in the CVD oxide film (12) is suppressed and, by not oxidizing the non-doped poly-silicon (13), a semiconductor apparatus is easily manufactured.

摘要翻译： 在形成沟槽（7）之前，用于形成n +源极层（11）的掩模由衬底的表面上的氮化物膜形成。 此时，确保衬底表面上的n +源层（11）的足够的宽度。 由此，得到n +源极层（11）与源电极（15）之间的稳定的接触。 在作为嵌入沟槽（7）中的栅电极（10a）的掺杂多晶硅上形成作为0.1微米以上且0.3微米以下的厚度的层间绝缘膜的CVD氧化膜（12） ，并且在CVD氧化膜（12）上形成未被氧化的未掺杂多晶硅（13）。 由此，抑制CVD氧化膜（12）中的空隙的产生，并且通过不氧化非掺杂多晶硅（13），容易制造半导体装置。

公开(公告)号：US08482061B2

公开(公告)日：2013-07-09

申请号：US13067575

申请日：2011-06-09

申请人： Takeyoshi Nishimura

发明人： Takeyoshi Nishimura

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L21/2253 ,  H01L21/26586 ,  H01L29/0878 ,  H01L29/1608 ,  H01L29/401 ,  H01L29/407 ,  H01L29/42368 ,  H01L29/66068 ,  H01L29/66666 ,  H01L29/66734 ,  H01L29/7827

摘要： A semiconductor device according to the invention includes p-type well region 3 and n+ source region 4, both formed selectively in the surface portion of n− drift region 2; trench 6 in contact with n+ source region 4 and extending through p-type well region 3 into n− drift region 2; field plate 8 formed in trench 6 with first insulator film 7 interposed between the trench 6 inner surface and field plate 8; gate electrode 10 formed in trench 6 with second insulator film 9 interposed between the trench 6 side wall and gate electrode 10, gate electrode 10 being formed above field plate 8; first insulator film 7 being thicker than second insulator film 9; and n−− lightly doped region 21 in n− drift region 2, n−− lightly doped region 21 crossing under the bottom surface of trench 6 from the corner portion thereof, n−− lightly doped region 21 covering the bottom surface of trench 6. The semiconductor device according to the invention and the method of manufacturing the semiconductor device according to the invention facilitate lowering the ON-state voltage, preventing the breakdown voltage from lowering, lowering the gate capacitance, and reducing the manufacturing costs.

摘要翻译： 根据本发明的半导体器件包括p型阱区3和n +源极区4，它们均选择性地形成在n漂移区2的表面部分中; 沟槽6，与n +源极区4接触并且通过p型阱区3延伸到n漂移区2中; 形成在沟槽6中的第一绝缘膜7设置在沟槽6内表面和场板8之间的场板8; 形成在沟槽6中的第二绝缘膜9设置在沟槽6侧壁和栅电极10之间的栅电极10，形成在场板8之上的栅电极10; 第一绝缘膜7比第二绝缘膜9厚; 和n-偏移区域2中的n-轻掺杂区域21，n - 轻掺杂区域21，其从其拐角部分在沟槽6的底表面下方交叉，n--覆盖沟槽6的底表面的轻掺杂区域21 根据本发明的半导体器件和根据本发明的半导体器件的制造方法便于降低导通状态电压，防止击穿电压降低，降低栅极电容并降低制造成本。

公开(公告)号：US5291050A

公开(公告)日：1994-03-01

申请号：US780222

申请日：1991-10-22

申请人： Takeyoshi Nishimura

发明人： Takeyoshi Nishimura

IPC分类号： H01L29/49 ,  H01L29/739 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L29/4983 ,  H01L29/7395

摘要： A metal-oxide-semiconductor (MOS) device designed to achieve reduced gate-to-drain capacitance is disclosed. The device has gate-electrode layer consisting of alternating polarity regions, such that regions of the gate-electrode layer not involved in channel operations have a conductivity type different from the conductivity type of the gate-electrode-layer regions actually involved in channel operations. Since the alternating conductivity regions form a capacitance in series to the gate-to-drain capacitance, the gate-to-drain capacitance of the device is reduced. An embodiment of the invention also incorporates increased-thickness regions of the gate-oxide film, which regions are disposed over semiconductor areas at which no channel operation occurs.

摘要翻译： 公开了一种设计用于实现降低的栅 - 漏电容的金属氧化物半导体（MOS）器件。 该器件具有由交替极性区域组成的栅电极层，使得不涉及沟道操作的栅电极层的区域具有与实际涉及沟道操作的栅电极层区域的导电类型不同的导电类型。 由于交变导电区域形成与栅极 - 漏极电容串联的电容，所以器件的栅极 - 漏极电容减小。 本发明的实施例还包括栅极氧化膜的增加厚度的区域，该区域设置在不发生沟道操作的半导体区域上。

公开(公告)号：US06246092B1

公开(公告)日：2001-06-12

申请号：US09042544

申请日：1998-03-17

申请人： Tatsuhiko Fujihira ,  Takeyoshi Nishimura ,  Takashi Kobayashi

发明人： Tatsuhiko Fujihira ,  Takeyoshi Nishimura ,  Takashi Kobayashi

IPC分类号： H03K1728

CPC分类号： H01L29/7808 ,  H01L27/0248 ,  H01L27/0629 ,  H01L29/402 ,  H01L29/7811 ,  H01L29/866 ,  H01L2924/0002 ,  H01L2924/00

摘要： A MOS type semiconductor apparatus is provided that includes a first MOS type semiconductor device through which main current flows, and a second MOS type semiconductor device through which current that is smaller than the main current flows. The first and second MOS type semiconductor devices provided on the same semiconductor substrate have substantially the same structure, and have a common drain electrode. A gate electrode of the second MOS type semiconductor device is connected to the common drain electrode. The semiconductor apparatus further includes a plurality of pairs of Zener diodes which are connected in series and provided between the source electrode of the second MOS type semiconductor device and the gate electrode of the first MOS type semiconductor device. Each pair of Zener diodes are reversely connected to each other.

摘要翻译： 提供一种MOS型半导体装置，其包括主电流流过的第一MOS型半导体器件和小于主电流的电流流过的第二MOS型半导体器件。 设置在同一半导体衬底上的第一和第二MOS型半导体器件具有基本上相同的结构，并且具有公共漏电极。 第二MOS型半导体器件的栅电极连接到公共漏电极。 半导体装置还包括串联连接并设置在第二MOS型半导体器件的源电极和第一MOS型半导体器件的栅电极之间的多对齐纳二极管。 每对齐纳二极管彼此反向连接。

公开(公告)号：US5869372A

公开(公告)日：1999-02-09

申请号：US555426

申请日：1995-11-09

申请人： Tatsuhiko Fujihira ,  Seiji Momota ,  Takeyoshi Nishimura ,  Kazutoshi Sugimura ,  Masao Yoshino ,  Takashi Kobayashi

发明人： Tatsuhiko Fujihira ,  Seiji Momota ,  Takeyoshi Nishimura ,  Kazutoshi Sugimura ,  Masao Yoshino ,  Takashi Kobayashi

IPC分类号： H01L21/28 ,  H01L21/265 ,  H01L21/266 ,  H01L21/306 ,  H01L21/316 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

CPC分类号： H01L21/823857 ,  H01L21/266

摘要： A semiconductor device manufacturing process is disclosed in which one processing step is reduced by replacing the photoresist film conventionally used for masking in the formation of the heavily doped n-type layer by an oxide film, and by monitoring, in the monitor region, the simultaneous formation of the contact holes in the oxide films different in the respective thickness thereof. An n+ region is formed by using a second insulation film and a polysilicon gate electrode formed on a semi-conductor wafer as masks for implanting arsenic ions. Further, a contact hole to be formed on a p-type region covered with a fourth insulation film and a second insulation film and a contact hole to be formed on the n+ region covered with the fourth insulation film are formed simultaneously under the monitoring of the formation of the contact holes in a monitor region.

摘要翻译： 公开了一种半导体器件制造方法，其中通过用氧化膜替代常规用于形成重掺杂n型层的掩模的光致抗蚀剂膜，并且通过在监测区域中监测同时 形成不同厚度的氧化膜中的接触孔。 通过使用形成在半导体晶片上的第二绝缘膜和多晶硅栅极作为用于注入砷离子的掩模来形成n +区。 此外，在被覆有第四绝缘膜的p型区域上形成的接触孔和被覆有第四绝缘膜的n +区域上形成的第二绝缘膜和接触孔同时形成在 在监视器区域中形成接触孔。

公开(公告)号：US5043779A

公开(公告)日：1991-08-27

申请号：US557178

申请日：1990-07-23

申请人： Takeyoshi Nishimura

发明人： Takeyoshi Nishimura

IPC分类号： H01L29/10 ,  H01L29/78

CPC分类号： H01L29/7802 ,  H01L29/1095

摘要： An MOS device where the avalanche breakdown strength may be increased without decreasing the on-resistance of the device is provided by decreasing the width of a high impurity concentration area in contact with one of the two electrodes to increase the curvature of the deepest part of the well region.

摘要翻译： 通过降低与两个电极中的一个接触的高杂质浓度区域的宽度来增加雪崩击穿强度而不降低器件的导通电阻的MOS器件，以增加器件的最深部分的曲率 井区。

公开(公告)号：US10484607B2

公开(公告)日：2019-11-19

申请号：US15893062

申请日：2018-02-09

申请人： Takeyoshi Nishimura ,  Naoto Asakura

发明人： Takeyoshi Nishimura ,  Naoto Asakura

IPC分类号： H04N5/232 ,  G02B27/64 ,  H04N5/378

摘要： A shake correction control device includes circuitry to control an ON/OFF timing of horizontal synchronizing signals of an image capture element, and an ON/OFF timing of one or more drive signals used for correcting a shake of the image capture element, shift at least one of the ON/OFF timing of the drive signals used for correcting the shake of the image capture element so as to be out of a period of time during which analog/digital (A/D) conversion processing is collectively performed on pixel signals for one or more horizontal lines of the image capture element, and adjust the at least one of the ON/OFF timing of the drive signals used for correcting the shake of the image capture element with respect to the horizontal synchronizing signals based on the number of the one or more horizontal lines of the pixel signals collectively subjected to the A/D conversion processing.