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37 条记录 (耗时 0.022 秒)

    Equalizer and reproduction signal processing device
    1.
    发明授权
    Equalizer and reproduction signal processing device 失效
    均衡器和再生信号处理装置

    公开(公告)号：US07321620B2

    公开(公告)日：2008-01-22

    申请号：US10383746

    申请日：2003-03-10

    申请人： Hiroyuki Nakahira ,  Koichi Nagano ,  Koji Okamoto ,  Akira Yamamoto

    发明人： Hiroyuki Nakahira ,  Koichi Nagano ,  Koji Okamoto ,  Akira Yamamoto

    IPC分类号： H03H7/30 ,  H03H7/40 ,  H03K5/159

    CPC分类号： H04L25/03038 ,  H04L2025/03477 ,  H04L2025/03585 ,  H04L2025/03617

    摘要： The present invention provides an equalizer capable of accurately compensating for non-linearity of an input signal due to the asymmetry phenomenon, etc., during the disk production process. Two tap coefficients are provided in a coefficient unit. A comparator compares the value of a middle tap signal, which is a reference signal, and a threshold, so as to produce a selection signal based on the comparison result. The coefficient unit selects one of the two tap coefficients as the selected tap coefficient based on the selection signal, and a tap signal is multiplied with the selected tap coefficient. Thus, it is possible to adaptively switch the tap coefficients of the equalizer as a whole based on the value of the middle tap signal, which is the reference signal. Therefore, it is possible to accurately compensate for the non-linearity of the input signal.

    摘要翻译： 本发明提供了一种均衡器，其能够在盘生产过程期间由于不对称现象等而精确地补偿输入信号的非线性。 在系数单元中提供两个抽头系数。 比较器将作为参考信号的中间抽头信号的值与阈值进行比较，以便基于比较结果产生选择信号。 系数单元基于选择信号选择两个抽头系数中的一个作为所选抽头系数，并且抽头信号与选择的抽头系数相乘。 因此，可以基于作为参考信号的中间抽头信号的值来自适应地切换均衡器的抽头系数作为整体。 因此，可以准确地补偿输入信号的非线性。

    SYNCHRONOUS CONTROL CIRCUIT AND VIDEO DISPLAY DEVICE
    3.
    发明申请
    SYNCHRONOUS CONTROL CIRCUIT AND VIDEO DISPLAY DEVICE 审中-公开
    同步控制电路和视频显示设备

    公开(公告)号：US20110043693A1

    公开(公告)日：2011-02-24

    申请号：US12885838

    申请日：2010-09-20

    申请人： Hiroyuki Nakahira ,  Takashi Yamamoto ,  Kouji Okamoto ,  Akira Yamamoto

    发明人： Hiroyuki Nakahira ,  Takashi Yamamoto ,  Kouji Okamoto ,  Akira Yamamoto

    IPC分类号： H04L7/00 ,  H04N9/475

    CPC分类号： H04L7/0337 ,  G09G5/008 ,  G09G2370/16 ,  H03L7/0812 ,  H04L7/0334

    摘要： A synchronization control circuit is provided with a first sampling means for sampling the envelope signal of the modulation signal at a first sampling timing, a second sampling means for sampling the envelope signal at a second sampling timing, a third sampling means for sampling the envelope signal at a third sampling timing, a phase error calculation means for calculating a phase error value indicating the amount of synchronization deviation between the modulation signal and the reference clock signal using the outputs of the first, second, and third sampling means, a delay control means for generating a delay control signal on the basis of the phase error value, and a delay generation means for generating the first, second, and third sampling timing by delaying the reference clock signal based on the delay control signal. Thereby, a synchronization control circuit that can reduce the circuit size required for obtaining the synchronization with relative to the Early/Late system can be provided.

    摘要翻译： 同步控制电路设置有第一采样装置，用于在第一采样定时对调制信号的包络信号进行采样，第二采样装置用于在第二采样定时采样包络信号;第三采样装置，用于对包络信号进行采样 在第三采样定时，使用相位误差计算装置，用于使用第一，第二和第三采样装置的输出来计算指示调制信号和参考时钟信号之间的同步偏差量的相位误差值;延迟控制装置 用于基于相位误差值产生延迟控制信号;以及延迟产生装置，用于通过基于延迟控制信号延迟参考时钟信号来产生第一，第二和第三采样定时。 因此，可以提供能够相对于Early / Late系统减小获得同步所需的电路尺寸的同步控制电路。

    Multilevel record modulator and demodulator
    8.
    发明授权
    Multilevel record modulator and demodulator 失效
    多级记录调制器和解调器

    公开(公告)号：US06778483B2

    公开(公告)日：2004-08-17

    申请号：US09984768

    申请日：2001-10-31

    申请人： Hiroki Mouri ,  Takashi Yamamoto ,  Hiroyuki Nakahira ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Takashi Yamamoto ,  Hiroyuki Nakahira ,  Akira Yamamoto

    IPC分类号： G11B576

    CPC分类号： G11B20/10009 ,  G11B20/1488 ,  H03M5/16 ,  H04L25/4923

    摘要： An encoding efficiency higher than 1 is achieved by accomplishing ternary recording on a recording medium. For this purpose, an 8-bit binary data word is converted to a 5-symbol ternary code word. A look-up table stores a modulation/demodulation table defining the correspondence between the binary data word (8B) and the ternary code word (5T). A table generating circuit generates the modulation/demodulation table to be stored in the look-up table such that each of constraints specified by a plurality of parameters is satisfied. If a PRML (Partial Response Maximum Likelihood) scheme is combined with an 8B5T code thus obtained, a signal-to-noise ratio is improved.

    摘要翻译： 通过在记录介质上进行三进制记录来实现高于1的编码效率。 为此，将8位二进制数据字转换为5符号三进制码字。 查找表存储定义二进制数据字（8B）和三进制码字（5T）之间的对应关系的调制/解调表。 表生成电路生成要存储在查找表中的调制/解调表，使得满足由多个参数指定的每个约束。 如果PRML（部分响应最大似然）方案与由此获得的8B5T码组合，则提高了信噪比。

    Adaptive digital filter
    9.
    发明授权
    Adaptive digital filter 失效
    自适应数字滤波器

    公开(公告)号：US06745218B1

    公开(公告)日：2004-06-01

    申请号：US09527404

    申请日：2000-03-16

    申请人： Akira Yamamoto ,  Hiroyuki Nakahira ,  Hirokuni Fujiyama ,  Hiroki Mouri

    发明人： Akira Yamamoto ,  Hiroyuki Nakahira ,  Hirokuni Fujiyama ,  Hiroki Mouri

    IPC分类号： G06F1710

    CPC分类号： H03H21/0012

    摘要： An adaptive digital filter of the present invention includes: a pipelined filtering section for performing a filtering operation based on input data and coefficient data so as to output filtered data; and a non-pipelined adaptation section for outputting the coefficient data to the pipelined filtering section by performing a coefficient adaptation operation in a non-pipelined process based on the input data and the filtered data so that the filtered data output from the pipelined filtering section converges to a predetermined reference value.

    摘要翻译： 本发明的自适应数字滤波器包括：流水线滤波部分，用于基于输入数据和系数数据执行滤波操作，以便输出滤波数据; 以及非流水线自适应部分，用于基于输入数据和滤波数据，通过在非流水线处理中执行系数自适应操作，将系数数据输出到流水线过滤部分，使得从流水线过滤部分输出的滤波数据收敛 到预定的参考值。

    Signal processor
    10.
    发明授权
    Signal processor 失效

    公开(公告)号：US07068584B2

    公开(公告)日：2006-06-27

    申请号：US10376247

    申请日：2003-03-03

    申请人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Akira Yamamoto

    发明人： Hiroki Mouri ,  Hiroyuki Nakahira ,  Akira Yamamoto

    IPC分类号： G11B7/00

    CPC分类号： G11B20/10046 ,  G11B20/10009 ,  G11B20/10296

    摘要： The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value. The control circuit compares the quality value calculated by the quality value calculating circuit with a predetermined reference value, and conducts a process for improving the quality value according to the comparison result.